參數(shù)資料
型號(hào): W9412G6CH-5
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 8M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝: 0.400 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66
文件頁數(shù): 19/55頁
文件大?。?/td> 2011K
代理商: W9412G6CH-5
W9412G6CH
Publication Release Date:Nov. 19, 2007
- 26 -
Revision A07
9.5 DC Characteristics
MAX.
SYM.
PARAMETER
-45
-5
-6
-75
UNIT NOTES
IDD0
Operating current: One Bank Active-Precharge; tRC = tRC min;
tCK = tCK min; DQ, DM and DQS inputs changing twice per
clock cycle; Address and control inputs changing once per
clock cycle
130
120
110
mA
7
IDD1
Operating current: One Bank Active-Read-Precharge; Burst =
2; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA; Address
and control inputs changing once per clock cycle.
140
130
120
7, 9
IDD2P
Precharge Power Down standby current: All Banks Idle; Power
down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ,
DQS and DM
20
IDD2N
Idle standby current: CS > VIH min; All Banks Idle; CKE >
VIH min; tCK = tCK min; Address and other control inputs
changing once per clock cycle; Vin > VIH min or Vin < VIL max
for DQ, DQS and DM
45
7
IDD3P
Active Power Down standby current: One Bank Active; Power
down mode; CKE < VIL max; tCK = tCK min
20
IDD3N
Active standby current: CS > VIH min; CKE > VIH min; One
Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM
and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
60
7
IDD4R
Operating current: Burst = 2; Reads; Continuous burst; One
Bank Active; Address and control inputs changing once per
clock cycle; CL=3; tCK = tCK min; IOUT = 0mA
180
170
160
7, 9
IDD4W
Operating current: Burst = 2; Write; Continuous burst; One
Bank Active; Address and control inputs changing once per
clock cycle; CL = 3; tCK = tCK min; DQ, DM and DQS inputs
changing twice per clock cycle
180
170
160
7
IDD5
Auto Refresh current: tRC = tRFC min
200
190
180
7
IDD6
Self Refresh current: CKE < 0.2V
3
IDD7
Random Read current: 4 Banks Active Read with activate
every 20nS, Auto-Precharge Read every 20 nS; Burst = 4;
tRCD = 3; IOUT = 0mA; DQ, DM and DQS inputs changing twice
per clock cycle; Address changing once per clock cycle
320
300
280
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