參數(shù)資料
型號: W9412G6CH-5
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 8M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝: 0.400 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66
文件頁數(shù): 29/55頁
文件大小: 2011K
代理商: W9412G6CH-5
W9412G6CH
Publication Release Date: Nov. 19, 2007
- 35 -
Revision A07
10.9 System Notes:
a. Pullup slew rate is characterized under the test conditions as shown in Figure 1.
VSSQ
50 Ω
Output
Test point
Figure 1: Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.
Figure 2: Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV ± 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV ± 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs
switching and only one output switching.
Example: For typical slew rate, DQ0 is switching
For minimum slew rate, all DQ bits are switching worst case pattern
For maximum slew rate, only one DQ is switching from either high to low, or low to high
The remaining DQ bits remain the same as for previous state
d. Evaluation conditions
Typical:
25
oC (T Ambient), VDDQ = nominal, typical process
Minimum:
70
oC (T Ambient), VDDQ = minimum, slow-slow process
Maximum:
0
oC (T Ambient), VDDQ = maximum, fast-fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and
voltage, over the entire temperature and voltage range. For a given output, it represents the
maximum difference between pullup and pulldown drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOP II package devices only.
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