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參數(shù)資料
| 型號： | W83L951DG |
| 廠商： | Nuvoton Technology Corporation of America |
| 文件頁數(shù)： | 59/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC EMBEDDED CNTRLR 128-LQFP |
| 標準包裝： | 90 |
| 系列： | W83 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 24MHz |
| 連通性： | 主機接口，PS/2，SMBus，UART/USART |
| 外圍設(shè)備： | PWM，WDT |
| 輸入/輸出數(shù)： | 104 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b; D/A 2x8b |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 128-LQFP |
| 包裝： | 托盤 |
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W83L951DG/W83L951FG
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Bit 0: PS2_T/R PS/2 Channel Transmit/Receive
This bit is only valid when PS2_EN=1 and sets the PS2 logic for automatic transmission or reception
when PS2_T/R equals HIGH or LOW respectively (This bit may be modified, after unsetting PS2_EN).
When set the PS/2 channel is enabled to transmit data. To properly initiate a transmit operation this bit
must be set prior to writing to the Transmit Register; writes are blocked to the Transmit Register when
this bit is not set.
Upon setting the PS2_T/R bit the channel will drive its CLK line low and then float the DATA line and
hold this state until a write occurs to the Transmit Register or until the PS2_T/R bit is cleared. Writing
to the Transmit Register initiates the transmit operation. KB controller drives the data line low and,
within 100us, floats the clock line (externally pulled high by the pull-up resistor) to signal to the
external PS/2 device that data is now available.
The PS2_T/R bit is cleared on the 11th clock edge of the transmission or if a Transmit Timeout error
condition occurs.
Note: If the PS2_T/R bit is set while the channel is actively receiving data prior to the rising
edge of the 10th (parity bit) clock edge the receive data is discarded. If this bit is not set prior
to the 10th clock signal then the receive data is saved in the Receive Register.
When the PS2_T/R bit is cleared the PS/2 channel is enabled to receive data. Upon clearing
this bit, whether RDATA_RDY=0 or no, the channel’s CLK and DATA will float waiting for the
external PS/2 device to signal the start of a transmission for receiving data. But if
RDATA_RDY=1, the hardware won’t generate interrupt to indicate finished receive data.
If the PS2_T/R bit is set while RDATA_RDY=1 then the channel’s DATA line will float but its
CLK line will be held low, holding off the peripheral, until the Receive Register is read.
6.3.1.4
PS/2 Status Registers (PS2STS) (Default Value:: 0000_0000)
Bit 7: Receiver Busy (RX_BUSY)
This bit is indicators for each of the three PS/2 Channels. When a RX_BUSY bit is set the associated
channel is actively receiving PS/2 data; when a RX_BUSY bit is clear the channel is idle.
Bit 6: Start Bit Detect (START_DEC)
This bit is set on detecting start bit of receive conditions. Writing high will clear this bit.
Bit 5: Transmitter Timeout (XMIT_TIMEOUT)
This bit is set on one of 3 transmit conditions, and in addition the channel’s CLK line is automatically
pulled low and held for a period of 300us(Input clock=24MHz) or 600us(Input clock=12MHz) following
assertion of the XMIT_TIMEOUT bit during which time the PS2_T/R is also held low:
When the transmitter bit time (time between falling edges) exceeds 300us(Input clock=24MHz) or
600us(Input clock=12MHz).
When the transmitter start bit is not received within 25ms(Input clock=24MHz) or 50ms(Input
clock=12MHz) from signaling a transmit start event.
If the time from the 1st (start, falling edge) bit to the 11th (stop, falling edge) bit exceeds 2ms.
Writing high will clear this bit.
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