- 44 - 6.3.1.2 PS/2 T/R DATA Registers (PS2DATA) (Default Value: 1111_1111) Transmit: The byte written to this register, wh" />
參數(shù)資料
型號(hào)： W83L951DG
廠商： Nuvoton Technology Corporation of America
文件頁(yè)數(shù)： 56/112頁(yè)
文件大?。?/td> 0K
描述： IC EMBEDDED CNTRLR 128-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： W83
核心處理器： 8051
芯體尺寸： 8-位
速度： 24MHz
連通性： 主機(jī)接口，PS/2，SMBus，UART/USART
外圍設(shè)備： PWM，WDT
輸入/輸出數(shù)： 104
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b; D/A 2x8b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 128-LQFP
包裝： 托盤(pán)
W83L951DG/W83L951FG
- 44 -
6.3.1.2
PS/2 T/R DATA Registers (PS2DATA) (Default Value: 1111_1111)
Transmit:
The byte written to this register, when PS2_T/R = 1 and PS2_EN = 1 and XMIT_BUSY = 0, is
transmitted automatically by the PS/2 channel control logic. On successful start of this transmission,
the PS2 logic will automatic set XMIT_BUSY to high. If PS2_T/R = 0 or PS2_EN = 0 or XMIT_BUSY =
1, then writes to this register are ignored.
On successful completion of this transmission or upon a Transmit Time-out condition the PS2_T/R
and XMIT_BUSY bit is automatically set to low. The PS2_T/R bit must be written to a HIGH before
initiating another transmission to the remote device.
Note:
Even if PS2_T/R = 1 and PS2_EN = 1 and XMIT_BUSY = 0, writing the transmit Register will
hold the current transmission if RDATA_RDY is set. The automatic PS2 logic forces data to
be read from the Receive Register before allowing a transmission.
An interrupt is generated on the high to low transition of XMIT_BUSY.
All bits of this register are write-only for transmit data, because you always read received data.
Receive:
When PS2_EN=1 and PS2_T/R=0, the PS2 Channel is set to automatically receive data on that
channel (both the CLK and DATA lines will float waiting for the peripheral to initiate a reception by
sending a start bit followed by the data bits). After a successful reception data is placed in this register
and the RDATA_RDY bit is set and the CLK line is forced low by the PS2 channel logic. RDATA_RDY
is cleared and the CLK line is released to hi-z following a read of this register. This automatically holds
off further receive transfers until the 8051 has had a chance to get the data.
Note:
The Receive Register is initialized to 0xFF after a Timeout has occurred.
The channel can be enabled to automatically transmit data (PS2_EN=1) by setting PS2_T/R
while RDATA_RDY is set, however a device (not include host) transmission can hold until the
data has been read from the Receive Register.
An interrupt is generated on the low to high transition of RDATA_RDY.
If a receive timeout (REC_TIMEOUT=1) or a transmit timeout (XMIT_TIMEOUT =1) occurs
the channel is busied (CLK held low) for 300us(Input clock=24MHz) or 600us(Input
clock=12MHz) (Hold Time) to guarantee that the peripheral aborts. Writing to the Transmit
Register will be allowed; however the data written will not be transmitted until the Hold Time
expires.
In the foregoing situation, RDATA_RDY won’t automatically clear.
相關(guān)PDF資料
PDF描述
X90100M8IZT1 IC DIGITAL CAPACITOR NV 8-MSOP
X9015WS8T1 IC XDCP SGL 32-TAP 10K 8-SOIC
X9110TV14I-2.7 IC XDCP SGL 1024TAP 100K 14TSSOP
X9111TV14I-2.7T1 IC XDCP SGL 1024TAP 100K 14TSSOP
X9116WS8T2 IC XDCP 16-TAP 10K CMOS 8-SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W83L951FG 制造商:WINBOND 制造商全稱:Winbond 功能描述:Mobile Keyboard and Embedded Controller
W84032K05M010 制造商:Woodhead Molex 功能描述:
W8413G38FT 制造商:Dynatech 功能描述:28v
W8-413G38FT 制造商:Dynatech 功能描述:28v
W84601 制造商:Performance Tool 功能描述:16 Blade Mini Feeler Gauge 制造商:PERFORMANCE TOOLS 功能描述:MINI FEELER GAUGE
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*