Publication Release Date: August 2006 - 89 - Revision 1.0 6.17.2.3 Flash Address High Byte Register (FADDH) (" />
參數(shù)資料
型號： W83L951DG
廠商： Nuvoton Technology Corporation of America
文件頁數(shù)： 106/112頁
文件大小： 0K
描述： IC EMBEDDED CNTRLR 128-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： W83
核心處理器： 8051
芯體尺寸： 8-位
速度： 24MHz
連通性： 主機(jī)接口，PS/2，SMBus，UART/USART
外圍設(shè)備： PWM，WDT
輸入/輸出數(shù)： 104
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b; D/A 2x8b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 128-LQFP
包裝： 托盤
W83L951DG/W83L951FG
Publication Release Date: August 2006
- 89 -
Revision 1.0
6.17.2.3
Flash Address High Byte Register (FADDH) (Default Value: 0000_0000)
Address [15:8] Input, Like A [15:8] Pin. Refer to next section for further details.
6.17.2.4
Flash Address Low Byte Register (FADDL) (Default Value: 0000_0000)
Address [7:0] Input, Like A [7:0] Pin. Refer to next section for further details.
6.17.2.5
Flash Data Register (FDATA) (Default Value: 0000_0000)
Write: Data Input
Read: Data Output
Like DQ [7:0] Pin. Refer to next section for further details.
6.17.3 Device Bus Operation
6.17.3.1
Read Mode
The read operation of the Internal Flash is controlled by #CE and #OE, both of which have to be low
for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the
chip is de-selected and only standby power will be consumed. #OE is the output control and is used to
gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is
high. Refer to the timing waveforms for further details.
6.17.3.2
Write Mode
Device erasure and programming are accomplished via the command register. The contents of the
register serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. The command register itself does not occupy any addressable memory location. The
register is a latch used to store the commands, along with the address and data information needed to
execute the command. The command register is written by bringing #WE to logic low state, while #CE
is at logic low state and #OE is at logic high state. Addresses are latched on the falling edge of #WE
or #CE, whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever
happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing
parameters.
6.17.3.3
Output Disable Mode
With the #OE input at a logic high level (VIH), output from the device is disabled. This will cause the
output pins to be in a high impedance state.
6.17.3.4
Write Pulse "Glitch" Protection
Noise pulses of less than 10 ns (typical) on #OE, #CE, or #WE will not initiate a write cycle.
6.17.4 Command Definitions
Device operations are selected by writing specific address and data sequences into the command
register. Writing incorrect address and data values or writing them in the improper sequence will reset
the device to the read mode. "Command Definitions" defines the valid register command sequences.
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