- 您現(xiàn)在的位置：買賣IC網 > PDF目錄245650 > W25Q64CVSSAG (WINBOND ELECTRONICS CORP) 64M X 1 SPI BUS SERIAL EEPROM, PDSO8 PDF資料下載
參數資料
| 型號： | W25Q64CVSSAG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 64M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.208 INCH, GREEN, SOIC-8 |
| 文件頁數： | 40/79頁 |
| 文件大?。?/td> | 1086K |
| 代理商： | W25Q64CVSSAG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁
W25Q64CV
Publication Release Date: April 01, 2011
- 45 -
Revision C
DO
(IO
1)
7.2.25 64KB Block Erase (D8h)
The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0) (see Figure 2). The Block
Erase instruction sequence is shown in Figure 23.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Block Erase cycle has finished the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be
executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0)
bits (see Status Register Memory Protection table).
/CS
CLK
DI
(IO
0)
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Instruction (D8h)
8
9
29
30
31
24-Bit Address
23
22
2
1
0
High Impedance
*
Mode 0
Mode 3
= MSB
*
Figure 23. 64KB Block Erase Instruction Sequence Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| WS32K32-100HC | 128K X 8 MULTI DEVICE SRAM MODULE, 100 ns, CHIP66 |
| WS128K32-25G4CE | 512K X 8 MULTI DEVICE SRAM MODULE, 25 ns, CQFP68 |
| WMS128K8L-35DEQE | 128K X 8 STANDARD SRAM, 35 ns, CDSO32 |
| WMF512K8X-120CLQ5 | 512K X 8 FLASH 5V PROM, 120 ns, CQCC32 |
| WF4M16-150DTI5 | 4M X 16 FLASH 5V PROM MODULE, 150 ns, CDSO56 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W25Q64CVSSAP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64CVSSIG | 功能描述:IC SPI FLASH 64MBIT 8-SOIC RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:SpiFlash® 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應商設備封裝:8-MFP 包裝:帶卷 (TR) |
| W25Q64CVSSIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64CVTCAG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64CVTCAP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
發(fā)布緊急采購，3分鐘左右您將得到回復。