參數(shù)資料
型號: W25Q64CVSSAG
廠商: WINBOND ELECTRONICS CORP
元件分類: PROM
英文描述: 64M X 1 SPI BUS SERIAL EEPROM, PDSO8
封裝: 0.208 INCH, GREEN, SOIC-8
文件頁數(shù): 30/79頁
文件大?。?/td> 1086K
代理商: W25Q64CVSSAG
W25Q64CV
- 36 -
M7-0
/CS
CLK
Mode 0
Mode 3
0
1
IO
0
IO
1
2
IO
2
IO
3
4
5
20
16
12
8
21
17
22
18
23
19
13
9
14
10
15
11
A23-16
6
7
4
0
5
1
6
2
7
3
A15-8
A7-0
4
0
5
1
6
2
7
3
Byte 1
Byte 2
4
0
5
1
4
0
5
1
4
6
2
7
3
6
2
7
3
5
6
7
IOs switch from
Input to Output
Byte 3
8
9
10
11
12
13
Dummy
Figure 15b. Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10)
Word Read Quad I/O with “8/16/32/64-Byte Wrap Around”
The Word Read Quad I/O instruction can also be used to access a specific portion within a page by
issuing a “Set Burst with Wrap” command prior to E7h. The “Set Burst with Wrap” command can either
enable or disable the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is
enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte
page. The output data starts at the initial address specified in the instruction, once it reaches the ending
boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary
automatically until /CS is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap
around section within a page. See 7.2.18 for detail descriptions.
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