參數(shù)資料
型號(hào): W25Q64CVSSAG
廠商: WINBOND ELECTRONICS CORP
元件分類: PROM
英文描述: 64M X 1 SPI BUS SERIAL EEPROM, PDSO8
封裝: 0.208 INCH, GREEN, SOIC-8
文件頁數(shù): 24/79頁
文件大小: 1086K
代理商: W25Q64CVSSAG
W25Q64CV
- 30 -
7.2.13 Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO0, IO1, IO2, and IO3. A Quad enable of Status Register-2 must be
executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE
must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the W25Q64CV
at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC
Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address
as shown in Figure 12. The dummy clocks allow the device's internal circuits additional time for setting up
the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins should be
high-impedance prior to the falling edge of the first data out clock.
/CS
CLK
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Instruction (6Bh)
High Impedance
8
9
10
28
29
30
32
33
34
35
36
37
38
39
4
0
24-Bit Address
23
22
21
3
2
1
0
*
31
/CS
CLK
Dummy Clocks
0
40
41
42
43
44
45
46
47
5
1
High Impedance
4
5
High Impedance
6
2
7
3
High Impedance
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
Byte 1
6
7
1
6
2
7
3
Byte 2
Byte 3
Byte 4
IO
0 switches from
Input to Output
IO
0
IO
1
IO
2
IO
3
IO
0
IO
1
IO
2
IO
3
= MSB
*
Figure 12. Fast Read Quad Output Instruction Sequence Diagram
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