參數(shù)資料
型號(hào)： W25Q64CVSSAG
廠商： WINBOND ELECTRONICS CORP
元件分類： PROM
英文描述： 64M X 1 SPI BUS SERIAL EEPROM, PDSO8
封裝： 0.208 INCH, GREEN, SOIC-8
文件頁(yè)數(shù)： 16/79頁(yè)
文件大?。?/td> 1086K
代理商： W25Q64CVSSAG
W25Q64CV
Publication Release Date: April 01, 2011
- 23 -
Revision C
(IO
0)
DO
(IO
1)
7.2.5
Write Enable (06h)
The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to a
1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block
Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write
Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input (DI)
pin on the rising edge of CLK, and then driving /CS high.
/CS
CLK
DI
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Mode 0
Mode 3
Instruction (06h)
High Impedance
Figure 4. Write Enable Instruction Sequence Diagram
7.2.6 Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in section 7.1 can also be written to as volatile bits. This
gives more flexibility to change the system configuration and memory protection schemes quickly without
waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-
volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status
Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable
for Volatile Status Register instruction (Figure 5) will not set the Write Enable Latch (WEL) bit, it is only
valid for the Write Status Register instruction to change the volatile Status Register bit values.
/CS
CLK
DI
(IO
0)
DO
(IO
1)
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Mode 0
Mode 3
Instruction (50h)
High Impedance
Figure 5. Write Enable for Volatile Status Register Instruction Sequence Diagram
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