參數(shù)資料
型號： UPD78053GK-XXX-BE9
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, FINE PITCH, PLASTIC, TQFP-80
文件頁數(shù)： 59/78頁
文件大?。?/td> 610K
代理商： UPD78053GK-XXX-BE9
62
PD78052, 78053, 78054, 78055, 78056, 78058
Data Sheet U12327EJ5V0DS00
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85
°C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data retention power
VDDDR
1.8
6.0
V
supply voltage
Data retention power
IDDDR
VDDDR = 1.8 V
0.1
10
A
supply current
When the subsystem clock is unused (XT1 = VDD)
and the feed-back resistor is disconnected
Release signal set time
tSREL
0
s
Oscillation stabilization
tWAIT
Release by RESET
217/fX
ms
wait time
Release by interrupt request
Note
ms
Note Selection of 212/fXX and 214/fXX to 217/fXX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time selection register (OSTS).
Remark
fXX: Main system clock frequency (fX or fX/2)
fX: Main system clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
tSREL
tWAIT
VDD
RESET
STOP instruction execution
STOP mode
Data retension mode
Internal reset operation
HALT mode
Operating mode
VDDDR
tSREL
tWAIT
VDD
STOP instruction execution
STOP mode
Data retension mode
HALT mode
Operating mode
Standby release signal
(interrupt request)
VDDDR
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
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