參數(shù)資料
型號(hào)： UPD78053GK-XXX-BE9
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, FINE PITCH, PLASTIC, TQFP-80
文件頁數(shù)： 31/78頁
文件大?。?/td> 610K
代理商： UPD78053GK-XXX-BE9
37
PD78052, 78053, 78054, 78055, 78056, 78058
Data Sheet U12327EJ5V0DS00
Main System Clock Oscillator Characteristics (TA = –40 to +85
°C, VDD = 2.0 to 6.0 V)
Resonator
Recommended Circuit
Parameter
Conditions
MIN.
TYP.
MAX.
Unit
Ceramic
Oscillation
VDD = Oscillation voltage range
1.0
5.0
MHz
resonator
frequency (fX)Note 1
Oscillation
After VDD reaches oscillation
4
ms
stabilization timeNote 2
voltage range MIN.
Crystal
Oscillation
1.0
5.0
MHz
resonator
frequency (fX)Note 1
Oscillation
VDD = 4.5 to 6.0 V
10
ms
stabilization timeNote 2
30
External
X1 input
1.0
5.0
MHz
clock
frequency (fX)Note 1
X1 input
85
500
ns
high-/low-level width
(tXH , tXL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation stabilization time has been secured by the program before switching back
to the main system clock.
X1
X2
C2
C1
IC
X1
X2
PD74HCU04
X1
X2
C2
C1
IC
R1
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