參數(shù)資料
型號： UPD78053GK-XXX-BE9
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, FINE PITCH, PLASTIC, TQFP-80
文件頁數(shù)： 46/78頁
文件大?。?/td> 610K
代理商： UPD78053GK-XXX-BE9
50
PD78052, 78053, 78054, 78055, 78056, 78058
Data Sheet U12327EJ5V0DS00
(iii) SBI mode (SCK0 ... Internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY3
VDD = 4.5 to 6.0 V
800
ns
3200
ns
SCK0 high-/low-level
tKH3,VDD = 4.5 to 6.0 V
tKCY3/2 – 50
ns
width
tKL3
tKCY3/2 – 150
ns
SB0, SB1 setup time
tSIK3
VDD = 4.5 to 6.0 V
100
ns
(to SCK0
↑)
300
ns
SB0, SB1 hold time
tKSI3
tKCY3/2
ns
(from SCK0
↑)
Delay time from SCK0
↓ tKSO3
R = 1 k
,VDD = 4.5 to 6.0 V
0
250
ns
to SB0, SB1 output
C = 100 pFNote
0
1000
ns
SB0, SB1
↓ from SCK0↑ tKSB
tKCY3
ns
SCK0
↓ from SB0, SB1↓ tSBK
tKCY3
ns
SB0, SB1 high-level
tSBH
tKCY3
ns
width
SB0, SB1 low-level
tSBL
tKCY3
ns
width
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.
(iv) SBI mode (SCK0 ... External clock input)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY4
VDD = 4.5 to 6.0 V
800
ns
3200
ns
SCK0 high-/low-level
tKH4,VDD = 4.5 to 6.0 V
400
ns
width
tKL4
1600
ns
SB0, SB1 setup time
tSIK4
VDD = 4.5 to 6.0 V
100
ns
(to SCK0
↑)
300
ns
SB0, SB1 hold time
tKSI4
tKCY4/2
ns
(from SCK0
↑)
Delay time from SCK0
↓ tKSO4
R = 1 k
,VDD = 4.5 to 6.0 V
0
300
ns
to SB0, SB1 output
C = 100 pFNote
0
1000
ns
SB0, SB1
↓ from SCK0↑ tKSB
tKCY4
ns
SCK0
↓ from SB0, SB1↓ tSBK
tKCY4
ns
SB0, SB1 high-level
tSBH
tKCY4
ns
width
SB0, SB1 low-level
tSBL
tKCY4
ns
width
SCK0 rise, fall time
tR4, tF4
When using external device
160
ns
expansion function
When not using external device
1000
ns
expansion function
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
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