參數(shù)資料
型號： UPD78053GK-XXX-BE9
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, FINE PITCH, PLASTIC, TQFP-80
文件頁數(shù)： 44/78頁
文件大?。?/td> 610K
代理商： UPD78053GK-XXX-BE9
49
PD78052, 78053, 78054, 78055, 78056, 78058
Data Sheet U12327EJ5V0DS00
(3) Serial interface (TA = –40 to +85
°C, VDD = 2.0 to 6.0 V)
(a) Serial interface channel 0
(i)
3-wire serial I/O mode (SCK0 ... Internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY1
4.5 V
≤ VDD ≤ 6.0 V
800
ns
2.7 V
≤ VDD < 4.5 V
1600
ns
3200
ns
SCK0 high-/low-level
tKH1,VDD = 4.5 to 6.0 V
tKCY1/2 – 50
ns
width
tKL1
tKCY1/2 – 100
ns
SI0 setup time (to
tSIK1
4.5 V
≤ VDD ≤ 6.0 V
100
ns
SCK0
↑)
2.7 V
≤ VDD < 4.5 V
150
ns
300
ns
SI0 hold time (from
tKSI1
400
ns
SCK0
↑)
SO0 output delay time
tKSO1
C = 100 pFNote
300
ns
from SCK0
↓
Note C is the load capacitance of the SO0 output line.
(ii) 3-wire serial I/O mode (SCK0 ... External clock input)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY2
4.5 V
≤ VDD ≤ 6.0 V
800
ns
2.7 V
≤ VDD < 4.5 V
1600
ns
3200
ns
SCK0 high-/low-level
tKH2,
4.5 V
≤ VDD ≤ 6.0 V
400
ns
width
tKL2
2.7 V
≤ VDD < 4.5 V
800
ns
1600
ns
SI0 setup time
tSIK2
100
ns
(to SCK0
↑)
SI0 hold time
tKSI2
400
ns
(from SCK0
↑)
Delay time from
tKSO2
C = 100 pFNote
300
ns
SCK0
↓ to SO0 output
SCK0 rise, fall time
tR2, tF2
When using external device
160
ns
expansion function
When not using external device
1000
ns
expansion function
Note C is the load capacitance of the SO0 output line.
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