參數(shù)資料
型號(hào)： UPD78053GK-XXX-BE9
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, FINE PITCH, PLASTIC, TQFP-80
文件頁數(shù)： 42/78頁
文件大?。?/td> 610K
代理商： UPD78053GK-XXX-BE9
47
PD78052, 78053, 78054, 78055, 78056, 78058
Data Sheet U12327EJ5V0DS00
(b) Except when MCS = 1, PCC2 to PCC0 = 000B (TA = –40 to +85
°C, VDD = 2.0 to 6.0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
VDD = 2.7 to 6.0 V
tCY – 80
ns
tCY – 150
ns
Address setup time
tADS
VDD = 2.7 to 6.0 V
tCY – 80
ns
tCY – 150
ns
Address hold time
tADH
VDD = 2.7 to 6.0 V
0.4tCY – 10
ns
0.37tCY – 40
ns
Data input time from address
tADD1
VDD = 2.7 to 6.0 V
(3 + 2n)tCY – 160
ns
(3 + 2n)tCY – 320
ns
tADD2
VDD = 2.7 to 6.0 V
(4 + 2n)tCY – 200
ns
(4 + 2n)tCY – 300
ns
Data input time from RD
↓
tRDD1
VDD = 2.7 to 6.0 V
(1.4 + 2n)tCY – 70
ns
(1.37 + 2n)tCY – 120
ns
tRDD2
VDD = 2.7 to 6.0 V
(2.4 + 2n)tCY – 70
ns
(2.37 + 2n)tCY – 120
ns
Read data hold time
tRDH
0ns
RD low-level width
tRDL1
VDD = 2.7 to 6.0 V
(1.4 + 2n)tCY – 20
ns
(1.37 + 2n)tCY – 20
ns
tRDL2
VDD = 2.7 to 6.0 V
(2.4 + 2n)tCY – 20
ns
(2.37 + 2n)tCY – 20
ns
Input time from RD
↓ to WAIT↓
tRDWT1
VDD = 2.7 to 6.0 V
tCY – 100
ns
tCY – 200
ns
tRDWT2
VDD = 2.7 to 6.0 V
2tCY – 100
ns
2tCY – 200
ns
Input time from WR
↓ to WAIT↓
tWRWT
VDD = 2.7 to 6.0 V
2tCY – 100
ns
2tCY – 200
ns
WAIT low-level width
tWTL
(1 + 2n)tCY
(2 + 2n)tCY
ns
Write data setup time
tWDS
VDD = 2.7 to 6.0 V
(2.4 + 2n)tCY – 60
ns
(2.37 + 2n)tCY – 100
ns
Write data hold time
tWDH
20
ns
WR low-level width
tWRL
VDD = 2.7 to 6.0 V
(2.4 + 2n)tCY – 20
ns
(2.37 + 2n)tCY – 20
ns
Delay time from ASTB
↓ to RD↓
tASTRD
VDD = 2.7 to 6.0 V
0.4tCY – 30
ns
0.37tCY – 50
ns
Delay time from ASTB
↓ to WR↓
tASTWR
VDD = 2.7 to 6.0 V
1.4tCY – 30
ns
1.37tCY – 50
ns
Remarks 1. MCS: Bit 0 of the oscillation mode selection register (OSMS)
2. PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC)
3. tCY = TCY/4
4. n indicates the number of waits.
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