參數(shù)資料
型號： UPD78053GK-XXX-BE9
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, FINE PITCH, PLASTIC, TQFP-80
文件頁數(shù)： 47/78頁
文件大小： 610K
代理商： UPD78053GK-XXX-BE9
51
PD78052, 78053, 78054, 78055, 78056, 78058
Data Sheet U12327EJ5V0DS00
(v) 2-wire serial I/O mode (SCK0 ... Internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY5
R = 1 k
,VDD = 2.7 to 6.0 V
1600
ns
C = 100 pFNote
3200
ns
SCK0 high-level width
tKH5
VDD = 2.7 to 6.0 V
tKCY5/2 – 160
ns
tKCY5/2 – 190
ns
SCK0 low-level width
tKL5
VDD = 4.5 to 6.0 V
tKCY5/2 – 50
ns
tKCY5/2 – 100
ns
SB0, SB1 setup time
tSIK5
4.5 V
≤ VDD ≤ 6.0 V
300
ns
(to SCK0
↑)
2.7 V
≤ VDD < 4.5 V
350
ns
400
ns
SB0, SB1 hold time
tKSI5
600
ns
(from SCK0
↑)
Delay time from SCK0
↓ tKSO5
0
300
ns
to SB0, SB1 output
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.
(vi) 2-wire serial I/O mode (SCK0 ... Internal clock input)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY6
VDD = 2.7 to 6.0 V
1600
ns
3200
ns
SCK0 high-level width
tKH6
VDD = 2.7 to 6.0 V
650
ns
1300
ns
SCK0 low-level width
tKL6
VDD = 2.7 to 6.0 V
800
ns
1600
ns
SB0, SB1 setup time
tSIK6
100
ns
(to SCK0
↑)
SB0, SB1 hold time
tKSI6
tKCY6/2
ns
(from SCK0
↑)
Delay time from SCK0
↓ tKSO6
R = 1 k
,VDD = 4.5 to 6.0 V
0
300
ns
to SB0, SB1 output
C = 100 pFNote
0
500
ns
SCK0 rise, fall time
tR6, tF6
When using external device
160
ns
expansion function
When not using external device
1000
ns
expansion function
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
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