參數(shù)資料
型號(hào): UPD78053GK-XXX-BE9
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, FINE PITCH, PLASTIC, TQFP-80
文件頁(yè)數(shù): 32/78頁(yè)
文件大?。?/td> 610K
代理商: UPD78053GK-XXX-BE9
38
PD78052, 78053, 78054, 78055, 78056, 78058
Data Sheet U12327EJ5V0DS00
Subsystem Clock Oscillator Characteristics (TA = –40 to +85
°C, VDD = 2.0 to 6.0 V)
Resonator
Recommended Circuit
Parameter
Conditions
MIN.
TYP.
MAX.
Unit
Crystal
Oscillation
32
32.768
35
kHz
resonator
frequency (fXT)Note 1
Oscillation
VDD = 4.5 to 6.0 V
1.2
2
s
stabilization timeNote 2
10
External
XT1 input
32
100
kHz
clock
frequency (fXT)Note 1
XT1 input
5
15
s
high-/low-level width
(tXTH , tXTL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem clock
is used.
XT1 XT2
C4
C3
R2
IC
XT1
XT2
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