參數(shù)資料
型號(hào)： UPD78053GK-XXX-BE9
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, FINE PITCH, PLASTIC, TQFP-80
文件頁數(shù)： 41/78頁
文件大?。?/td> 610K
代理商： UPD78053GK-XXX-BE9
46
PD78052, 78053, 78054, 78055, 78056, 78058
Data Sheet U12327EJ5V0DS00
(2) Read/write operation
(a) When MCS = 1, PCC2 to PCC0 = 000B (TA = –40 to +85
°C, VDD = 4.5 to 6.0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.85tCY – 50
ns
Address setup time
tADS
0.85tCY – 50
ns
Address hold time
tADH
50
ns
Data input time from address
tADD1
(2.85 + 2n)tCY – 80
ns
tADD2
(4 + 2n)tCY – 100
ns
Data input time from RD
↓
tRDD1
(2 + 2n)tCY – 100
ns
tRDD2
(2.85 + 2n)tCY – 100
ns
Read data hold time
tRDH
0ns
RD low-level width
tRDL1
(2 + 2n)tCY – 60
ns
tRDL2
(2.85 + 2n)tCY – 60
ns
Input time from RD
↓ to WAIT↓
tRDWT1
0.85tCY – 50
ns
tRDWT2
2tCY – 60
ns
Input time from WR
↓ to WAIT↓
tWRWT
2tCY – 60
ns
WAIT low-level width
tWTL
(1.15 + 2n)tCY
(2 + 2n)tCY
ns
Write data setup time
tWDS
(2.85 + 2n)tCY – 100
ns
Write data hold time
tWDH
20
ns
WR low-level width
tWRL
(2.85 + 2n)tCY – 60
ns
Delay time from ASTB
↓ to RD↓
tASTRD
25
ns
Delay time from ASTB
↓ to WR↓
tASTWR
0.85tCY + 20
ns
Delay time from RD
↑ to ASTB↑ at
tRDAST
0.85tCY – 10
1.15tCY + 20
ns
external fetch
Address hold time from RD
↑ at
tRDADH
0.85tCY – 50
1.15tCY + 50
ns
external fetch
Write data output time from RD
↑
tRDWD
40
ns
Write data output time from WR
↓
tWRWD
050
ns
Address hold time from WR
↑
tWRADH
0.85tCY
1.15tCY + 40
ns
Delay time from WAIT
↑ to RD↑
tWTRD
1.15tCY + 40
3.15tCY + 40
ns
Delay time from WAIT
↑ to WR↑
tWTWR
1.15tCY + 30
3.15tCY + 30
ns
Remarks 1. MCS: Bit 0 of the oscillation mode selection register (OSMS)
2. PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC)
3. tCY = TCY/4
4. n indicates the number of waits.
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