
CHAPTER 6 CLOCK GENERATION FUNCTION
User’s Manual U12768EJ4V1UD
151
6.6
Cautions on Power Save Function
(1) While an instruction is being executed on internal ROM
To set the power save mode (IDLE mode or software STOP mode) while an instruction is being executed on the
internal ROM, insert a NOP instruction as a dummy instruction to correctly execute the routine after releasing the
power save mode.
The following shows the sequence of setting the power save mode.
<1>
Disable DMA operation.
<2>
Disable interrupts (set NP bit of PSW to 1).
<3>
Write 8-bit data to the command register (PRCMD).
<4>
Write setting data to the power save control register (PSC) (using the following instructions).
Store instruction (ST/SST instruction)
Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
<5>
Clear the interrupt disabled state (re-set the NP bit of the PSW to 0).
<6>
Insert NOP instructions (2 or 5 instructions).
<7>
If DMA operation is necessary, enable DMA operation.
Cautions 1. Insert two NOP instructions if the ID bit value of the PSW is not changed by the execution of
the instruction that clears the NP bit to 0 (<5>), and insert five NOP instructions if changed.
The following shows a description example.
[Description example] : When using PSC register
LDSR rX.5
; NP bit = 1
ST.B r0, PRCMD[r0]
; Write to PRCMD
ST.B rD, RSC[r0]
; PSC register setting
LDSR rY, 5
; NP bit = 0
NOP
; Dummy instructions (2 or 5 instructions)
:
NOP
(next instruction)
; Execution routine after releasing IDLE/software STOP
mode
:
rX: Value to be written to PSW
rY: Value to be rewritten to PSW
rD: Value to be set to PSC
When saving the PSW value, transfer the PSW value before setting the NP bit to the rY
register.
2. The instructions (<5> interrupt disable clear, <6> NOP instruction) following the store
instruction to the PSC register for setting the IDLE mode and software STOP mode are
executed before entering the power save mode.