
CHAPTER 11 A/D CONVERTER
User’s Manual U12768EJ4V1UD
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11.2 Configuration
The A/D converter consists of the following hardware.
Table 11-1. Configuration of A/D Converter
Item
Configuration
Analog input
12 channels (ANI0 to ANI11)
Registers
Successive approximation register (SAR)
A/D conversion result register (ADCR)
A/D conversion result register H (ADCRH): only higher 8 bits can be
read
Control registers
A/D converter mode register (ADM)
Analog input channel specification register (ADS)
(1) Successive approximation register (SAR)
This register compares the voltage value of the analog input signal with the voltage tap (compare voltage) value
from the series resistor string, and holds the result of the comparison starting from the most significant bit (MSB).
When the comparison result has been stored down to the least significant bit (LSB) (i.e., when the A/D conversion
has been completed), the contents of the SAR are transferred to the A/D conversion result register.
(2) A/D conversion result register (ADCR), A/D conversion result register H (ADCRH)
Each time A/D conversion is completed, the result of the conversion is loaded to this register from the successive
approximation register. The higher 10 bits of this register hold the result of the A/D conversion (the lower 6 bits
are fixed to 0). This register is read using a 16-bit memory manipulation instruction. RESET input sets ADCR to
0000H.
When using only the higher 8 bits of the result of the A/D conversion, ADCRH is read using an 8-bit memory
manipulation instruction.
RESET input sets ADCRH to 00H.
(3) Sample & hold circuit
The sample & hold circuit samples each of the analog input signals sequentially sent from the input circuit, and
sends the sampled data to the voltage comparator. This circuit also holds the sampled analog input signal voltage
during A/D conversion.
(4) Voltage comparator
The voltage comparator compares the analog input signal with the output voltage of the series resistor string.
(5) Series resistor string
The series resistor string is connected between AVREF and AVSS and generates a voltage for comparison with the
analog input signal.