參數(shù)資料
型號(hào)： TMX470R1A64PN
廠商： Texas Instruments, Inc.
英文描述： 16/32-Bit RISC Flash Microcontroller
中文描述： 16/32位RISC閃存微控制器
文件頁(yè)數(shù)： 8/46頁(yè)
文件大小： 381K
代理商： TMX470R1A64PN
www.ti.com
A
TMS470R1A64
16/32-Bit RISC Flash Microcontroller
SPNS099–NOVEMBER 2004
Table 2. Terminal Functions (continued)
TERMINAL
INTERNAL
PULLUP/
PULLDOWN
(3)
TYPE
(1)(2)
DESCRIPTION
NAME
PIN
NUMBER
3.3-V
REF I
GND
REF I
3.3-V
PWR
GND
AD
REFHI
65
MibADC module high-voltage reference input
AD
REFLO
66
MibADC module low-voltage reference input
V
CCAD
67
MibADC analog supply voltage
V
SSAD
68
MibADC analog ground reference
SERIAL PERIPHERAL INTERFACE 1 (SPI1)
SPI1 clock. SPI1CLK can be programmed as a GIO pin.
SPI1 chip enable. SPI1ENA can be programmed as a GIO pin.
SPI1 slave chip select. SPI1SCS can be programmed as a GIO pin.
IPD
SPI1 data stream. Slave in/master out. SPI1SIMO can be programmed as a
GIO pin.
SPI1 data stream. Slave out/master in. SPI1SOMI can be programmed as a
GIO pin.
SERIAL PERIPHERAL INTERFACE 2 (SPI2)
SPI2 clock. SPI2CLK can be programmed as a GIO pin.
SPI2 chip enable. SPI2ENA can be programmed as a GIO pin.
SPI2 data stream. Slave in/master out. SPI2SIMO can be programmed as a
IPD
GIO pin.
SPI2 data stream. Slave out/master in. SPI2SOMI can be programmed as a
GIO pin.
ZERO-PIN PHASE-LOCKED LOOP (ZPLL)
Crystal connection pin or external clock input
External crystal connection pin
Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator
becomes the system clock. If not in bypass mode, TI recommends that
IPD
PLLDIS be connected to ground or pulled down to ground by an external
resistor.
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
IPD
SCI1 clock. SCI1CLK can be programmed as a GIO pin.
IPU
SCI1 data receive. SCI1RX can be programmed as a GIO pin.
IPU
SCI1 data transmit. SCI1TX can be programmed as a GIO pin.
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
IPU
SCI2 data receive. SCI2RX can be programmed as a GIO pin.
IPU
SCI2 data transmit. SCI2TX can be programmed as a GIO pin.
SYSTEM MODULE (SYS)
Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output of
IPD
SYSCLK, ICLK, or MCLK.
Input master chip power-up reset. External V
CC
monitor circuitry must assert a
IPD
power-on reset.
Bidirectional reset. The internal circuitry can assert a reset, and an external
system reset can assert a device reset.
IPU
On RST, the output buffer is implemented as an open drain (drives low only.
To ensure an external reset is not arbitrarily generated, TI recommends that
an external pullup resistor be connected to RST.
SPI1CLK
SPI1ENA
SPI1SCS
SPI1SIMO
5
1
2
3
3.3-V I/O
SPI1SOMI
4
SPI2CLK
SPI2ENA
SPI2SIMO
33
36
34
3.3-V I/O
SPI2SOMI
35
OSCIN
OSCOUT
PLLDIS
8
7
41
1.8-V I
1.8-V O
3.3-V I
SCI1CLK
SCI1RX
SCI1TX
51
53
52
3.3-V I/O
3.3-V I/O
3.3-V I/O
SCI2RX
SCI2TX
25
26
3.3-V I/O
3.3-V I/O
CLKOUT
48
3.3-V I/O
PORRST
16
3.3-V I
RST
10
3.3-V I/O
8
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