參數(shù)資料
型號(hào)： TMX470R1A64PN
廠商： Texas Instruments, Inc.
英文描述： 16/32-Bit RISC Flash Microcontroller
中文描述： 16/32位RISC閃存微控制器
文件頁(yè)數(shù)： 7/46頁(yè)
文件大?。?/td> 381K
代理商： TMX470R1A64PN
www.ti.com
A
TMS470R1A64
16/32-Bit RISC Flash Microcontroller
SPNS099–NOVEMBER 2004
Table 2. Terminal Functions
TERMINAL
INTERNAL
PULLUP/
PULLDOWN
(3)
TYPE
(1)(2)
DESCRIPTION
NAME
PIN
NUMBER
HIGH-END TIMER (HET)
HET[0]
HET[2]
HET[4]
HET[6]
HET[7]
HET[8]
HET[12]
HET[14]
HET[16]
HET[18]
HET[20]
HET[22]
HET[24]
72
77
78
79
80
45
15
14
13
39
38
37
27
The A64 device has both the logic and registers for a full 32-I/O HET
implemented, even though not all 32 pins are available externally
Timer input capture or output compare. The HET[31:0] applicable pins can be
programmed as general-purpose input/output (GIO) pins.
HET pins [22, 20, 18, 16, 14, 12, 8, 7, 6, 4, 2, and 0] are high-resolution pins
for A64. HET[24] is a standard-resolution pin.
3.3-V I/O
IPD
The high-resolution (HR) SHARE feature allows even-numbered HR pins to
share the next higher odd-numbered HR pin structures. This HR sharing is
independent of whether or not the odd-numbered pin is available externally. If
an odd-numbered pin is available externally and shared, then the odd pin can
only be used as a general-purpose I/O. For more information on HR SHARE,
see the
TMS470R1x High-End Timer Reference Guide
(literature number
SPNU199).
STANDARD CAN CONTROLLER (SCC)
SCC receive pin or GIO pin
IPU
SCC transmit pin or GIO pin
CLASS II SERIAL INTERFACE (C2SIA)
IPD
C2SIa module loopback enable pin or GIO pin
C2SIa module receive data input pin or GIO pin
IPD
C2SIa module transmit data output pin or GIO pin
GENERAL-PURPOSE I/O (GIO)
CANSRX
CANSTX
49
50
3.3-V I/O
3.3-V I/O
C2SIaLPN
C2SIaRX
C2SIaTX
28
30
29
3.3-V I/O
3.3-V I/O
3.3-V I/O
GIOA[0]/INT
0
GIOA[1]/INT
1/ECLK
GIOA[4]/
INT4
GIOA[5]/
INT5
GIOA[6]/
INT6
GIOA[7]/
INT7
23
3.3-V I
24
General-purpose input/output pins. GIOA[0]/INT[0] is an input-only pin.
GIOA[7:0]/INT[7:0] are interrupt-capable pins.
20
IPD
The GIOA[1]/INT[1]/ECLK pin is multiplexed with the external clock-out
function of the external clock prescale (ECP) module.
19
3.3-V I/O
GIOA[2]/INT[2] and GIOA[3]/INT[3]] pins are not applicable on the A64 device.
18
17
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)
3.3-V I/O
MibADC event input. ADEVT can be programmed as a GIO pin.
MibADC analog input pins
ADEVT
ADIN[0]
ADIN[2]
ADIN[4]
ADIN[6]
ADIN[8]
ADIN[10]
ADIN[12]
ADIN[14]
56
60
59
58
57
64
62
63
61
The A64 device has only 8 input channels but all S/W registers are capable.
ADIN[15,13, 11, 9, 7, 5, 3, and 1] pins are not applicable to the A64 device.
IPD
3.3-V I
(1)
(2)
(3)
I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST
state.)
7
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