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參數資料
| 型號： | TMX470R1A64PN |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16/32-Bit RISC Flash Microcontroller |
| 中文描述： | 16/32位RISC閃存微控制器 |
| 文件頁數： | 5/46頁 |
| 文件大?。?/td> | 381K |
| 代理商： | TMX470R1A64PN |
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A
Device Characteristics
The TMS470R1A64 device is a derivative of the F05 system emulation device SE470R1VB8AD. Table 1
identifies all the characteristics of the TMS470R1A64 device except the SYSTEM and CPU, which are generic.
TMS470R1A64
16/32-Bit RISC Flash Microcontroller
SPNS099–NOVEMBER 2004
Table 1. Device Characteristics
CHARACTERISTICS
DEVICE DESCRIPTION
COMMENTS
MEMORY
For the number of memory selects on this device, see the "Memory Selection Assignment" table (Table 3).
Flash is pipeline-capable.
64K-Byte Flash
4K-Byte SRAM
INTERNAL MEMORY
The A64 RAM is implemented in one 4K array selected by two mem-
ory-select signals (see the "Memory Selection Assignment" table, Table 3).
PERIPHERALS
For the device-specific interrupt priority configurations, see the "Interrupt Priority" table (Table 6). For the 1K peripheral address ranges and
their peripheral selects, see the "A64 Peripherals, System Module, and Flash Base Addresses" table (Table 5).
CLOCK
ZPLL
Zero-pin PLL has no external loop filter pins.
5 I/O
Port A has 6 external pins - GIOA[2]/INT2 and GIOA[3]/INT3 are not
GENERAL-PURPOSE I/Os
1 Input only
available.
ECP
YES
C2SIa
1
1 (3-pin)
SCI2 has no external clock pin, only transmit/receive pins (SCI2TX and
SCI
1 (2-pin)
SCI2RX)
CAN (HECC and/or SCC)
1 SCC
Standard CAN controller
SPI (5-pin, 4-pin or 3-pin)
1 (5-pin)
SPI2 has no chip select pin.
1 (4-pin)
The A64 device has both the logic and registers for a full 32-I/O HET
implemented, even though not all 32 pins are available externally.
The high-resolution (HR) SHARE feature allows even HR pins to share the
next higher odd HR pin structures. This HR sharing is independent of
whether or not the odd pin is available externally. If an odd pin is available
externally and shared, then the odd pin can only be used as a gen-
eral-purpose I/O. For more information on HR SHARE, see the
TMS470R1x
High-End Timer (HET) Reference Guide
(literature number SPNU199).
HET with XOR Share
13 I/O
HET RAM
64-Instruction Capacity
10-bit, 8-channel
64-word FIFO
1.71 - 2.05 V
3.0–3.6 V
80
PN
8-channel MibADC. Both the logic and registers for a full 16-channel
MibADC are present.
MibADC
CORE VOLTAGE
I/O VOLTAGE
PINS
PACKAGE
5
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