參數(shù)資料
型號： TMX470R1A64PN
廠商： Texas Instruments, Inc.
英文描述： 16/32-Bit RISC Flash Microcontroller
中文描述： 16/32位RISC閃存微控制器
文件頁數(shù)： 33/46頁
文件大?。?/td> 381K
代理商： TMX470R1A64PN
www.ti.com
A
SPIn SLAVE MODE TIMING PARAMETERS
SPIn SLAVE MODE EXTERNAL TIMING PARAMETERS
(CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)
(1)(2)(3)(4)
(see Figure 14)
TMS470R1A64
16/32-Bit RISC Flash Microcontroller
SPNS099–NOVEMBER 2004
NO.
1
MIN
100
MAX
UNIT
ns
t
c(SPC)S
Cycle time, SPInCLK
(5)
256t
c(ICLK)
0.5t
+
0.25t
c(ICLK)
0.5t
+
0.25t
c(ICLK)
0.5t
+
0.25t
c(ICLK)
0.5t
+
0.25t
c(ICLK)
0.5t
c(SPC)S
-
0.25t
c(ICLK)
0.5t
c(SPC)S
-
0.25t
c(ICLK)
0.5t
c(SPC)S
-
0.25t
c(ICLK)
0.5t
c(SPC)S
-
0.25t
c(ICLK)
t
w(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 0)
2
(6)
ns
t
w(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
t
w(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
3
(6)
ns
t
w(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
t
d(SPCH-
SOMI)S
t
d(SPCL-
SOMI)S
t
v(SPCH-
SOMI)S
t
v(SPCL-
SOMI)S
t
su(SIMO-
SPCL)S
t
su(SIMO-
SPCH)S
t
v(SPCL-
SIMO)S
t
v(SPCH-
SIMO)S
Delay time, SPInCLK high to SPInSOMI valid
(clock polarity = 0)
Delay time, SPInCLK low to SPInSOMI valid
(clock polarity = 1)
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 0)
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 1)
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 0)
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 1)
6 + t
r
4
(6)
ns
6 + t
f
t
c(SPC)S
- 6 - t
r
5
(6)
ns
t
c(SPC)S
- 6 - t
f
6
6
(6)
ns
6
6
7
(6)
ns
6
(1)
(2)
(3)
(4)
(5)
The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
If the SPI is in slave mode, the following must be true: t
≥
(PS + 1) t
, where PS = prescale value set in SPInCTL1.[12:5].
For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
t
= interface clock cycle time = 1 /f
When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t
c(SPC)S
≥
(PS +1)t
c(ICLK)
≥
100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0: t
= 2t
≥
100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
(6)
33
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