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參數(shù)資料
| 型號： | TMX470R1A64PN |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16/32-Bit RISC Flash Microcontroller |
| 中文描述： | 16/32位RISC閃存微控制器 |
| 文件頁數(shù)： | 12/46頁 |
| 文件大小： | 381K |
| 代理商： | TMX470R1A64PN |
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www.ti.com
A
TMS470R1A64
16/32-Bit RISC Flash Microcontroller
SPNS099–NOVEMBER 2004
Flash read
The A64 Flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to
0xFFE0_0000. The Flash is addressed through memory selects 0 and 1.
NOTE:
The Flash external pump voltage (VCCP) is required for all operations (program,
erase, and read).
Flash pipeline mode
When in pipeline mode, the Flash operates with a system clock frequency of up to 48 MHz (versus a system
clock in normal mode of up to 24 MHz). Flash in pipeline mode is capable of accessing 64-bit words and
provides two 32-bit pipelined words to the CPU. Also in pipeline mode, the Flash can be read with no wait states
when memory addresses are contiguous (after the initial 1-or 2-wait-state reads).
NOTE:
After a system reset, pipeline mode is
disabled
(ENPIPE bit [FMREGOPT.0] is a 0).
In other words, the A64 device powers up and comes out of reset in non-pipeline
mode. Furthermore, setting the Flash configuration mode bit (GLBCTRL.4) will
override pipeline mode.
Flash program and erase
The A64 device Flash has one 64K-byte bank that consists of five sectors. These five sectors are shown in
Table 4.
Table 4. Flash Sectors
SECTOR NO.
0
1
2
3
4
SEGMENT
8K Bytes
8K Bytes
16K Bytes
16K Bytes
16K Bytes
LOW ADDRESS
0x0000_0000
0x0000_2000
0x0000_4000
0x0000_8000
0x0000_C000
HIGH ADDRESS
0x0000_1FFF
0x0000_3FFF
0x0000_7FFF
0x0000_BFFF
0x0000_FFFF
The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit
word.
NOTE:
The Flash external pump voltage (V
CCP
) is required for all operations (program, erase,
and read).
For more detailed information on Flash program and erase operations, see the
TMS470R1x F05 Flash
Reference Guide
(literature number SPNU213).
HET RAM
The A64 device contains HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is configurable
by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET RAM is
addressed through memory select 4.
XOR share
The A64 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution
channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more
detailed information on the HET XOR-share feature, see the
TMS470R1x High-End Timer (HET) Reference
Guide
(literature number SPNU199).
12
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