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參數(shù)資料
| 型號： | TMX470R1A64PN |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16/32-Bit RISC Flash Microcontroller |
| 中文描述： | 16/32位RISC閃存微控制器 |
| 文件頁數(shù)： | 25/46頁 |
| 文件大小： | 381K |
| 代理商： | TMX470R1A64PN |
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A
ZPLL and clock specifications
TIMING REQUIREMENTS FOR ZPLL CIRCUITS ENABLED OR DISABLED
SWITCHING CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS FOR
CLOCKS
(1)(2)
TMS470R1A64
16/32-Bit RISC Flash Microcontroller
SPNS099–NOVEMBER 2004
MIN
MAX
UNIT
MHz
ns
ns
ns
kHz
f
(OSC)
t
c(OSC)
t
w(OSCIL)
t
w(OSCIH)
f
(OSCRST)
Input clock frequency
Cycle time, OSCIN
Pulse duration, OSCIN low
Pulse duration, OSCIN high
OSC FAIL frequency
(1)
4
20
50
15
15
53
(1)
Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1)
bits equal to 1. For more detailed information on these bits and device resets, see the
TMS470R1x System Module Reference Guide
(literature number SPNU189).
PARAMETER
TEST CONDITIONS
(3)
Pipeline mode enabled
Pipeline mode disabled
MIN
MAX
UNIT
MHz
f
(SYS)
System clock frequency
(4)
48
24
24
25
24
25
24
f
(CONFIG)
f
(ICLK)
System clock frequency - Flash config mode
Interface clock frequency
MHz
MHz
Pipeline mode enabled
Pipeline mode disabled
Pipeline mode enabled
Pipeline mode disabled
Pipeline mode enabled
Pipeline mode disabled
f
(ECLK)
External clock output frequency for ECP Module
MHz
t
c(SYS)
Cycle time, system clock
20.8
41.6
41.6
40
41.6
40
41.6
ns
t
c(CONFIG)
t
c(ICLK)
Cycle time, system clock - Flash config mode
Cycle time, interface clock
ns
ns
Pipeline mode enabled
Pipeline mode disabled
Pipeline mode enabled
Pipeline mode disabled
t
c(ECLK)
Cycle time, ECP module external clock output
ns
(1)
f
= M
×
f
/ R, where M = {4 or 8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the
CLKDIVPRE [2:0] bits in the global control register (GLBCTRL.[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the
GLBCTRL register (GLBCTRL.3).
f
(SYS)
= f
(OSC)
/ R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f
= f
/ X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1]
bits in the SYS module.
f
= f
/ N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
Flash Vread must be set to 5V to achieve maximum System Clock Frequency.
(2)
(3)
(4)
25
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