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參數(shù)資料
| 型號： | TMX470R1A64PN |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16/32-Bit RISC Flash Microcontroller |
| 中文描述： | 16/32位RISC閃存微控制器 |
| 文件頁數(shù)： | 11/46頁 |
| 文件大?。?/td> | 381K |
| 代理商： | TMX470R1A64PN |
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A
memory selects
TMS470R1A64
16/32-Bit RISC Flash Microcontroller
SPNS099–NOVEMBER 2004
Memory selects allow the user to address memory arrays (i.e., Flash, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that, together, define the array's starting (base) address, block size, and protection.
The base address of each memory select is configurable to any memory address boundary that is a multiple of
the decoded block size. For more information on how to control and configure these memory select registers, see
the bus structure and memory sections of the
TMS470R1x System Module Reference Guide
(literature number
SPNU189).
For the memory selection assignments and the memory selected, see Table 3.
Table 3. Memory Selection Assignment
MEMORY
SELECT
0 (fine)
1 (fine)
2 (fine)
3 (fine)
4 (fine)
MEMORY SELECTED
(ALL INTERNAL)
FLASH
FLASH
RAM
RAM
HET RAM
MEMORY
SIZE
MEMORY BASE
ADDRESS REGISTER
MFBAHR0 and MFBALR0
MFBAHR1 and MFBALR1
MFBAHR2 and MFBALR2
MFBAHR3 and MFBALR3
MFBAHR4 and MFBALR4
STATIC MEM
CTL REGISTER
MPU
NO
NO
YES
YES
64K
4K
(1)
1K
SMCR1
(1)
The starting addresses for both RAM memory-select signals
cannot
be offset from each other by a multiple of the user-defined block
size in the memory-base address register.
RAM
The A64 device contains 4K bytes of internal static RAM configurable by the SYS module to be addressed within
the range of 0x0000_0000 to 0xFFE0_0000. This A64 RAM is implemented in one 4K array selected by two
memory-select signals. This A64 configuration imposes an additional constraint on the memory map for RAM;
the starting addresses for both RAM memory selects cannot be offset from each other by the multiples of the
size of the physical RAM (i.e., 4K for the A64 device). The A64 RAM is addressed through memory selects 2 and
3.
The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user
finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an
operating system while allowing access to the current task. For more detailed information on the MPU portion of
the SYS module and memory protection, see the memory section of the
TMS470R1x System Module Reference
Guide
(literature number SPNU189).
F05 Flash
The F05 Flash memory is a nonvolatile electrically erasable and programmable memory implemented with a
32-bit-wide data bus interface. The F05 Flash has an external state machine for programming and erase
functions. See the
Flash read
and
Flash program and erase
sections below.
Flash protection keys
The
gram/erase/compaction operations from occurring until after the four protection keys have been matched by the
CPU loading the correct user keys into the FMPKEY control register. The protection keys on the A64 are located
in the last 4 words of the first 8K sector. For more detailed information on the Flash protection keys and the
FMPKEY control register, see the protection keys portions of the
TMS470R1x F05 Flash Reference Guide
(literature number SPNU213).
A64
devices
provide
Flash
protection
keys.
These
four
32-bit
protection
keys
prevent
pro-
11
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