參數(shù)資料
型號(hào)： TMX470R1A64PN
廠商： Texas Instruments, Inc.
英文描述： 16/32-Bit RISC Flash Microcontroller
中文描述： 16/32位RISC閃存微控制器
文件頁數(shù)： 14/46頁
文件大?。?/td> 381K
代理商： TMX470R1A64PN
www.ti.com
A
interrupt priority
TMS470R1A64
16/32-Bit RISC Flash Microcontroller
SPNS099–NOVEMBER 2004
The central interrupt manager (CIM) portion of the SYS module manages the interrupt requests from the device
modules (i.e., SPI1 or SPI2, SCI1 or SCI2, and RTI, etc.).
Although the CIM can accept up to 32 interrupt request signals, the A64 device only uses 21 of those interrupt
request signals. The request channels are maskable so that individual channels can be selectively disabled. All
interrupt requests can be programmed in the CIM to be of either type:
Fast interrupt request (FIQ)
Normal interrupt request (IRQ)
The precedences of request channels decrease with ascending channel order in the CIM (0, highest, and 31,
lowest, priority). For these channel priorities and the associated modules, see Table 6.
Table 6. Interrupt Priority
MODULES
SPI1
RTI
RTI
RTI
SPI2
GIO
Reserved
HET
Reserved
SCI1/SCI2
SCI1
C2SIa
Reserved
Reserved
SCC
Reserved
MibADC
SCI2
Reserved
Reserved
SCI1
System
Reserved
HET
Reserved
SCC
SCI2
MibADC
Reserved
GIO
MibADC
Reserved
INTERRUPT SOURCES
INTERRUPT LEVEL/CHANNEL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
SPI1 end-transfer/overrun
COMP2 interrupt
COMP1 interrupt
TAP interrupt
SPI2 end-transfer/overrun
Interrupt A
Interrupt A
SCI1/SCI2 error interrupt
SCI1 receive interrupt
C2SIa interrupt
Interrupt A
End event conversion
SCI2 receive interrupt
SCI1 transmit interrupt
SW interrupt (SSI)
Interrupt B
Interrupt B
SCI2 transmit interrupt
End Group 1 conversion
Interrupt B
End Group 2 conversion
14
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