參數(shù)資料
型號: TMS320C241FNS
元件分類: 數(shù)字信號處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號處理器
文件頁數(shù): 94/116頁
文件大?。?/td> 1485K
代理商: TMS320C241FNS
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
94
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
external memory interface readtimings
switching characteristics over recommended operating conditions for an external memory
interface read (see Figure 38)
PARAMETER
MIN
MAX
UNIT
td(COL–CNTL)
td(COL–CNTH)
td(COL–A)RD
td(COH–RDL)
Delay time, CLKOUT low to control valid
3
ns
Delay time, CLKOUT low to control inactive
3
ns
Delay time, CLKOUT low to address valid
5
ns
Delay time, CLKOUT high to RD strobe active
4
ns
td(COL–RDH)
Delay time, CLKOUT low to RD strobe inactive high
–4
0
ns
td(COL–SL)
Delay time, CLKOUT low to STRB strobe active low
3
ns
td(COL–SH)
Delay time, CLKOUT low to STRB strobe inactive high
3
ns
th(A)COL
tsu(A)RD
th(A)RD
Hold time, address valid after CLKOUT low
–4
ns
Setup time, address valid before RD strobe active low
22
ns
Hold time, address valid after RD strobe inactive high
–1
ns
timing requirements [H = 0.5t
c(CO)
] (see Figure 38)
MIN
MAX
UNIT
ta(A)
Access time, read data from address valid
2H–20
ns
tsu(D)RD
th(D)RD
Setup time, read data before RD strobe inactive high
12
ns
Hold time, read data after RD strobe inactive high
0
ns
th(AIV-D)
Hold time, read data after address invalid
–3
ns
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