參數(shù)資料
型號: TMS320C241FNS
元件分類: 數(shù)字信號處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號處理器
文件頁數(shù): 78/116頁
文件大?。?/td> 1485K
代理商: TMS320C241FNS
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
78
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
external reference crystal/clock with PLL circuit enabled
The internal oscillator is enabled by connecting a crystal across XTAL1/CLKIN and XTAL2 pins as shown in
Figure 20a. The crystal should be in fundamental operation and parallel resonant, with an effective series
resistance of 30 and a power dissipation of 1 mW; it should be specified at a load capacitance of 20 pF.
timings with the PLL circuit enabled
PARAMETER
MIN
TYP
MAX
UNIT
MHz
fx
Input clock frequency
Oscillator
1
5
CLKIN
1
5
MHz
C1, C2
Load capacitance
10
pF
switching characteristics over recommended operating conditions [H = 0.5 t
c(CO)
] (see Figure 21)
PARAMETER
CLOCK MODE
MIN
TYP
MAX
UNIT
tc(CO)
tf(CO)
tr(CO)
tw(COL)
tw(COH)
Cycle time, CLKOUT
50
ns
Fall time, CLKOUT
4
ns
Rise time, CLKOUT
4
ns
Pulse duration, CLKOUT low
H–3
H
H+3
ns
Pulse duration, CLKOUT high
H –3
H
H+3
ns
tp
Transition time, PLL synchronized after PLL enabled
before PLL lock,
CLKIN multiply by 4
2500tc(Cl)
ns
timing requirements (see Figure 21)
EXTERNAL REFERENCE
CRYSTAL
MIN
MAX
UNIT
tc(Cl)
tf(Cl)
tr(Cl)
tw(CIL)
tw(CIH)
Cycle time, XTAL1/CLKIN
5 MHz
200
ns
Fall time, XTAL1/CLKIN
5
ns
Rise time, XTAL1/CLKIN
5
ns
Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl)
Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl)
40
60
%
40
60
%
XTAL1/CLKIN
CLKOUT
tc(CI)
tw(CIL)
tw(CIH)
tw(COL)
tw(COH)
tc(CO)
tf(Cl)
tr(Cl)
tr(CO)
tf(CO)
Figure 21. CLKIN-to-CLKOUT Timing for PLL Oscillator Mode, Multiply-by-4 Option with 5-MHz Clock
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