參數(shù)資料
型號： TMS320C241FNS
元件分類： 數(shù)字信號處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號處理器
文件頁數(shù)： 16/116頁
文件大?。?/td> 1485K
代理商： TMS320C241FNS
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions - ’F241 PG and FN Packages (Continued)
NAME
64
QFP
NO.
68
PLCC
NO.
TYPE
RESET
STATE
DESCRIPTION
CLOCK SIGNALS (CONTINUED)
CLKOUT
/IOPD0
5
12
I/O
O
Clock output. This pin outputs either the CPU clock (CLKOUT) or the
watchdog clock (WDCLK). The selection is made by the CLKSRC bit (bit 14)
of the System Status and Control Register (SSCR). This pin can be used as
a GPIO if not used as a clock output pin.
TEST SIGNALS
TCK
28
36
I
I
JTAG test clock with internal pullup
TDI
29
37
I
I
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK.
TDO
30
38
O
I
JTAG scan out, test data output (TDO). The contents of the selected register
(instruction or data) is shifted out of TDO on the falling edge of TCK.
TMS
31
39
I
I
JTAG test-mode select (TMS) with internal pullup. This serial control input is
clocked into the TAP controller on the rising edge of TCK.
TRST
32
40
I
I
JTAG test reset with internal pulldown. TRST, when driven high, gives the
scan system control of the operations of the device. If this signal is not
connected or driven low, the device operates in its functional mode, and the
test reset signals are ignored.
EMU0
37
48
I/O
I
Emulator I/O pin 0 with internal pullup. When TRST is driven high, this pin is
used as an interrupt to or from the emulator system and is defined as
input/output through the JTAG scan.
EMU1
38
49
I/O
I
Emulator I/O pin 1 with internal pullup. When TRST is driven high, this pin is
used as an interrupt to or from the emulator system and is defined as
input/output through JTAG scan.
SUPPLY SIGNALS
VDD
9
16
–
–
Digital logic supply voltage (5 V)
41
52
–
–
–
42
–
–
VDDO
1
8
–
–
Digital logic and buffer supply voltage (5 V)
34
45
–
–
51
62
–
–
–
41
–
–
VSS
10
17
–
–
Digital logic ground reference
40
51
–
–
–
43
–
–
2
9
–
–
VSSO
26
34
–
–
Digital logic and buffer ground reference
33
44
–
–
50
61
–
–
NO CONNECT
NC
–
27
No internal connection made to this pin
DNC
I = input, O = output, Z = high impedance
The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.
§ In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.
NOTE:
Bold, italicized pin names
indicate pin function after reset.
25
33
–
–
Do not connect. Reserved for test.
相關(guān)PDF資料
PDF描述
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