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參數(shù)資料
| 型號(hào)： | TMS320C241FNS |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 34/116頁(yè) |
| 文件大小： | 1485K |
| 代理商： | TMS320C241FNS |
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TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
34
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
clock generation
The ’F243/’F241 devices have an on-chip, (x4) PLL-based clock module. This module provides all the
necessary clocking signals for the device, as well as control for low-power mode entry. The only external
component necessary for this module is a fundamental crystal. The “times 4” (x4) option for the ’F243/’F241
PLL is fixed and cannot be changed.
The PLL-based clock module provides two modes of operation:
Crystal-operation
This mode allows the use of a 5-MHz external reference crystal to provide the time base to the device.
External clock source operation
This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external
clock source input on the XTAL1/CLKIN pin. In this case, an external oscillator clock is connected to the
XTAL1/CLKIN pin.
The clock module includes two external pins:
1.
XTAL1/CLKIN
clock source/crystal input
2.
XTAL2
output to crystal
áááá
áááá
áááá
áááá
áááá
áááá
áááá
XTAL2
XTAL1/CLKIN
áááá
áááá
áááá
áááá
áááá
áááá
áááá
CPUCLK
Figure 7. PLL Clock Module Block Diagram
low-power modes
The ’24x has an IDLE instruction. When executed, the IDLE instruction stops the clocks to all circuits in the CPU,
but the clock output from the CPU continues to run. With this instruction, the CPU clocks can be shut down to
save power while the peripherals (clocked with CLKOUT) continue to run. The CPU exits the IDLE state if it is
reset, or, if it receives an interrupt request.
clock domains
All ’24x-based devices have two clock domains:
1.
CPU clock domain – consists of the clock for most of the CPU logic
2.
System clock domain – consists of the peripheral clock (which is derived from CLKOUT of the CPU) and
the clock for the interrupt logic in the CPU.
When the CPU goes into IDLE mode, the CPU clock domain is stopped while the system clock domain continues
to run. This mode is also known as IDLE1 mode. The ’24x CPU also contains support for a second IDLE mode,
IDLE2. By asserting IDLE2 to the ’24x CPU, both the CPU clock domain and the system clock domain are
stopped, allowing further power savings. A third low-power mode, HALT mode, the deepest, is possible if the
oscillator and WDCLK are also shut down when in IDLE2 mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMS320C241PGS | 16-Bit Digital Signal Processor |
| TMS320F241FNQ | 16-Bit Digital Signal Processor |
| TMS320F241PGQ | 16-Bit Digital Signal Processor |
| TMS320F243PGEQ | 16-Bit Digital Signal Processor |
| TMS320F243PGES | 16-Bit Digital Signal Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320C241PGS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| TMS320C242 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLER |
| TMS320C242FN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLER |
| TMS320C242FNA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| TMS320C242FNS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
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