參數(shù)資料
型號: TMS320C241FNS
元件分類: 數(shù)字信號處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號處理器
文件頁數(shù): 80/116頁
文件大?。?/td> 1485K
代理商: TMS320C241FNS
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
80
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
RS timings
switching characteristics over recommended operating conditions for a reset [H = 0.5t
c(CO)
]
(see Figure 25)
PARAMETER
MIN
MAX
UNIT
tw(RSL1)
td(EX)
The parameter tw(RSL1) refers to the time RS is an output.
Pulse duration, RS low
8tc(CO)
36H
ns
Delay time, reset vector executed after RS high
ns
A0–A15
CLKOUT
RS
XTAL1/
CLKIN
tw(RSL1)
td(EX)
Figure 25. Watchdog Reset Pulse
timing requirements for a reset [H = 0.5t
c(CO)
] (see Figure 26)
MIN
MAX
UNIT
tw(RSL)
Pulse duration, RS low
5
ns
td(EX)
The parameter tw(RSL) refers to the time RS is an input
Delay time, reset vector executed after RS high
36H
ns
RS
XTAL1/
CLKIN
A0–A15
CLKOUT
Case A. Power-on reset
tw(RSL) + x§
td(EX)
RS
XTAL1/
CLKIN
CLKOUT
A0–A15
Case B. External reset after power-on
tw(RSL) + x§
td(EX)
§The value of x depends on the reset condition as follows:
PLL enabled:
Assuming CLKIN is stable, x=PLL lock-up time. If the internal oscillator
is used, x=oscillator lock-up time + PLL lock-up time. In case of resets after power on reset, x=0 (i.e., tw(RSL)=8H ns only).
Figure 26. Reset Timing
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