
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
75
POST OFFICE BOX 1443 
 HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
VLOAD
IOL
CT
IOH
Output
Under
Test
50 
Where:
IOL
IOH
VLOAD
CT
=
=
=
=
2 mA (all outputs)
300 
μ
A (all outputs)
1.5 V
110-pF typical load-circuit capacitance
Figure 17. Test Load Circuit
signal transition levels
The data in this section is shown for the 5-V version. Note that some of the signals use different reference
voltages, see the recommended operating conditions table. TTL-output levels are driven to a minimum
logic-high level of 2.4 V and to a maximum logic-low level of 0.7 V.
Figure 18 shows the TTL-level outputs.
0.7 V  (VOL)
20%
2.4 V  (VOH)
80%
Figure 18. TTL-Level Outputs
TTL-output transition times are specified as follows:
For a high-to-low transition the level at which the output is said to be no longer high is below 80% of the
total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage
range and lower.
For a low-to-high transition the level at which the output is said to be no longer low is 20% of the total voltage
range and higher and the level at which the output is said to be high is 80% of the total voltage range and
higher.
Figure 19 shows the TTL-level inputs.
0.7 V  (VIL)
10%
2.0 V  (VIH)
90%
Figure 19. TTL-Level Inputs
TTL-compatible input transition times are specified as follows:
For a high-to-low transitionon an input signal, the level at which the input is said to be no longer high is 90%
of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage
range and lower.
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10%
of the total voltage range and higher and the level at which the input is said to be high is 90% of the total
voltage range and higher.