
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
90
POST OFFICE BOX 1443 
 HOUSTON, TEXAS 77251–1443
SPI SLAVE MODE TIMING PARAMETERS
Slave mode timing information is listed in the following tables.
SPI slave mode external timing parameters (clock phase = 0)
 (see Figure 36)
NO.
MIN
MAX
UNIT
12
tc(SPC)S
tw(SPCH)S
tw(SPCL)S
tw(SPCL)S
tw(SPCH)S
Cycle time, SPICLK
4tc(CO)
0.5tc(SPC)S–10
0.5tc(SPC)S–10
0.5tc(SPC)S–10
0.5tc(SPC)S–10
ns
13§
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
ns
Pulse duration, SPICLK low (clock polarity = 1)
14§
Pulse duration, SPICLK low (clock polarity = 0)
ns
Pulse duration, SPICLK high (clock polarity = 1)
15§
td(SPCH-SOMI)S
Delay time, SPICLK high to SPISOMI valid
(clock polarity = 0)
0.375tc(SPC)S–10
ns
td(SPCL-SOMI)S
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
0.375tc(SPC)S–10
16§
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =0)
0.75tc(SPC)S
ns
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =1)
0.75tc(SPC)S
19§
tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
0
ns
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
0
20§
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
0.5tc(SPC)S
ns
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
0.5tc(SPC)S
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc = system clock cycle time = 1/CLKOUT = tc(CO)
§The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).