
Samsung ASIC
5-6
STDM110
SPSRAM_LP
Low-Power Single-Port Synchronous Static RAM
Logic Symbol
Function Description
SPSRAM_LP is a single-port synchronous static RAM which is provided as a compiler. SPSRAM_LP is
intended for use in low-power applications. On the rising edge of CK, the write cycle is initiated when WEN
is low and CSN is low. The data on DI[] is written into the memory location specified on A[]. During the write
cycle, DOUT[] remains stable. On the rising edge of CK, the read cycle is initiated when WEN is high and
CSN is low. The data at DOUT[] become valid after a delay. While in standby mode that CSN is high, A[] and
DI[] are disabled, data stored in the memory is retained and DOUT[] remains stable. When OEN is high,
DOUT[] is placed in a high-impedance state.
Parameter Description
SPSRAM_LP is the compiler that automatically generates symbol, netlist, timing model, power model and
layout according to the following parameters; Number of words(w), Number of bit per word(b), Column
mux(y) and Number of banks(ba).
CK
X
X
↑
↑
CSN
X
H
L
L
WEN
X
X
L
H
OEN
H
L
L
L
A
X
X
DI
X
X
DOUT
Z
DOUT(t-1)
DOUT(t-1)
MEM(A)
COMMENT
Unconditional tri-state output
De-selected (standby mode)
Write cycle
Read Cycle
Valid
Valid
Valid
X
CK
CSN
WEN
OEN
A [m-1:0]
DI [b–1:0]
spsram_lp_<w>x<b>m<y>b<ba>
DOUT [b–1:0]
NOTES:
1. Words(w) is the number of words in SPSRAM_LP.
2. Bpw(b) is the number of bits per word.
3. Ymux(y) is one of the lower address decoder types.
4. Banks(ba) is the number of banks.
5. m =
log
2
w
Features
Suitable for low-power application
Separated data I/O
Synchronous operation
Asynchronous tristate output
Latched inputs and outputs
Automatic power-down mode available
Self-controlled circuit available
Zero standby current
Low noise output optimization
Flexible aspect ratio
Dual-bank scheme available
Up to 256Kbits capacity
Up to 16K number of words
Up to 128 number of bit per word