
Introduction
1.11 VDD/VSS Rules And Guidelines
Samsung ASIC
1-39
STDM110
1.11
V
DD
/V
SS
Rules
And Guidelines
There are three kinds of VDD and VSS in STDM110, providing power to internal
and I/O area.
Core logic
– VDD1I, VSS1I
Pre-driver (I/O area)
– VDD2P, VDD3P, VSS2P, VSS3P
Output-drive (I/O area)
– VDD2O, VDD3O, VSS2O, VSS3O
The number of VDD and VSS pads required for a specific design depends on the
following factors:
Number of input and output buffers
Number of simultaneous switching outputs
Number of used gates and simultaneous switching gates
Operating frequency
1.11.1 BASIC PLACEMENT GUIDELINES
The purpose of these guidelines is to minimize IR drop and noise for reliable
device operations.
Core logic and pre-driver V
DD
/V
SS
pads should be evenly distributed on all
sides of the chip.
If you have core block demanding high power (compiled memory, analog),
extra power pads should be placed on that side.
Power pads for SSO group should be evenly distributed in the SSO group.
Do not place the quiet signal (analog, reference) or analog power (VDDA/
VSSA) or bi-directional buffer next to a SSO group.
The opposite types of power pads (V
DD
/V
SS
) should be placed as close as
possible.
If it is possible, do not place power pads (V
DD
/V
SS
) at the corner of the chip.
1.11.2 VDD1I/VSS1I ALLOCATION GUIDELINES
The purpose of these guidelines is to ensure that the minimum number of core
logic power pad pairs meeting the electromigration current limit are used. The
number of VDD1I/VSS1I pads required for a specific design is determined by the
function of the operating frequency of a chip.
VDD1I bus width and the number of pads are equal to those of VSS1I
VDD1I/VSS1I buses and pads should be distributed evenly in the core and
on each side of the chip.
The total number of core logic VDD1I pads is equal to that of VSS1I pads.