STDM110
4-12
Samsung ASIC
PvIS/PvISD/PvISU
LVCMOS Schmitt Trigger Level Input Buffers
Cell Availability
Logic Symbol
2.5V Interface
3.3V Interface
5V Tolerant
PIS/PISD/PISU
PHIS/PHISD/PHISU
PTIS/PTISD/PTISU
Truth Table
PAD
1
0
1
Standard Load (SL)
Cell Name
PIS/PISD/PISU
PHIS/PHISD/PHISU
PTIS/PTISD/PTISU
PI
1
x
0
Y
1
0
1
PO
0
1
1
PI
2.835
2.835
2.835
Y
PO
PI
PAD
Y
PO
PI
PAD
Y
PO
PI
PAD
PIS
PISD
PISU
