
Introduction
1.10 Power Dissipation
Samsung ASIC
1-37
STDM110
1.10.3 DYNAMIC (AC) POWER DISSIPATION
When a CMOS gate changes its state, it draws switching current as a result of charging or discharging a load
capacitance, C
L
. The energy associated with the switching current for a node capacitance, C
L
, is
where V
DD
is the power supply voltage.
In addition to the power dissipated by the load capacitance, CMOS circuits consume power due to the short-
circuit current flowing through a temporary V
DD
-to-ground path during switching.
The dynamic power dissipation for an entire chip is much more complicated to estimate since it depends on the
degree of switching activity of the circuit. Samsung has found that the degree of switching activity is 10% on the
average and recommends this number to be used in estimating the total dynamic power dissipation.
1.10.4 POWER DISSIPATION IN STDM110
This section describes the equations on how to estimate the power dissipation in STDM110. As explained in the
previous section, the total power dissipation (P
TOTAL
) consists of static power dissipation (P
DC
) and dynamic
power dissipation (P
AC
).
P
TOTAL
= P
AC
+ P
DC
P
DC
is negligible in case of CMOS logic.
The dynamic power dissipation is caused by three components: input buffers (P
AC_INPUT
), output buffers
(P
AC_OUTPUT
), bidirectional buffers (P
AC_BI
), and internal cells (P
AC_INTERNAL
).
P
AC
= P
AC_ INPUT
+ P
AC_OUTPUT
+ P
AC_BI
+ P
AC_INTERNAL
Each term mentioned above is characterized by the following equations:
C
L
V
DD
2
×
P
AC_INPUT
[mW]
2.5
I
j_eq_p
F
100
--------- S
j
×
3.3
+
j
N_2.5V_input
∑
×
I
k_eq_p
F
100
--------- S
k
×
6.25
+
k
N_3.3V_input
∑
0.001 S
i
F
i
C
i_inload
×
×
(
)
i
N_total_input
∑
×
×
=
P
AC_OUTPUT
[mW]
2.5
I
i_eq_p
F
100
--------- S
i
×
3.3
+
i
N_2.5V_output
∑
×
I
j_eq_p
F
100
--------- S
j
×
j
N_3.3V_output
∑
+
×
=
6.25
0.001 S
i
F
i
C
i_outload
×
×
(
)
10.89
+
0.001 S
j
F
j
C
j_outload
×
×
(
)
j
N_3.3V_output
∑
×
i
N_2.5V_output
∑
×
P
AC_BI
[mW]
P
AC_BI_INPUT
×
1 S
out
–
(
)
P
AC_BI_OUTPUT
S
out
+
×
=
P
AC_BI_INPUT
[mW]
2.5
I
j_eq_p
F
100
j
×
×
j
N_2.5V_bi
∑
3.3
I
k_eq_p
F
100
k
×
×
6.25
+
k
N_3.3V_bi
∑
0.001 S
i
F
i
C
i_inload
×
×
(
)
i
N_total_bi
∑
×
×
+
×
=
P
AC_BI_OUTPUT
[mW]
2.5
I
i_eq_p
F
100
--------- S
i
×
i
N_2.5V_bi
∑
3.3
I
j_eq_p
F
100
--------- S
j
×
+
j
N_3.3V_bi
∑
×
+
×
=
6.25
0.001 S
i
F
i
C
i_outload
×
×
(
)
i
N_2.5V_bi
∑
×
10.89
0.001 S
i
F
i
C
i_outload
×
×
(
)
j
N_3.3V_bi
∑
×
+
P
AC_INTERNAL
[mW]
0.001
0.1118 S 0.0080
+
(
)
×
G F
0.001 P
i
F
i
×
(
)
j
N_macro
∑
+
×
=