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參數(shù)資料
| 型號： | ST7DALI |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | ADC |
| 英文描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI |
| 中文描述： | 8位單電壓閃存存儲器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，定時器，SPI和大理微控制器 |
| 文件頁數(shù)： | 91/141頁 |
| 文件大小： | 2175K |
| 代理商： | ST7DALI |
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ST7DALI
91/141
10-BIT A/D CONVERTER (ADC)
(Cont’d)
11.6.3.2 Input Voltage Amplifier
The input voltage can be amplified by a factor of 8
by enabling the AMPSEL bit in the ADCDRL regis-
ter.
When the amplifier is enabled, the input range is
0V to V
DD
/8.
For example, if V
DD
= 5V, then the ADC can con-
vert voltages in the range 0V to 430mV with an
ideal resolution of 0.6mV (equivalent to 13-bit res-
olution with reference to a V
SS
to V
DD
range).
For more details, refer to the Electrical character-
istics section.
Note:
The amplifier is switched on by the ADON
bit in the ADCCSR register, so no additional start-
up time is required when the amplifier is selected
by the AMPSEL bit.
11.6.3.3 Digital A/D Conversion Result
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V
AIN
) is greater than V
DDA
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
If the input voltage (V
AIN
) is lower than V
SSA
(low-
level voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD-
CDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
R
AIN
is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
11.6.3.4 A/D Conversion
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the I/O
ports chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the ADCCSR register:
– Select the CS[2:0] bits to assign the analog
channel to convert.
ADC Conversion mode
In the ADCCSR register:
Set the ADON bit to enable the A/D converter and
to start the conversion. From this time on, the
ADC performs a continuous conversion of the
selected channel.
When a conversion is complete:
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
To read the 10 bits, perform the following steps:
1. Poll EOC bit
2. Read ADCDRL
3. Read ADCDRH. This clears EOC automati-
cally.
To read only 8 bits, perform the following steps:
1. Poll EOC bit
2. Read ADCDRH. This clears EOC automati-
cally.
11.6.4 Low Power Modes
Note:
The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions.
11.6.5 Interrupts
None.
Mode
WAIT
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilization time
t
STAB
(see Electrical Characteristics)
before accurate conversions can be
performed.
HALT
1
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