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參數資料
| 型號： | ST7DALI |
| 廠商： | 意法半導體 |
| 元件分類： | ADC |
| 英文描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI |
| 中文描述： | 8位單電壓閃存存儲器，數據EEPROM，模數轉換器，定時器，SPI和大理微控制器 |
| 文件頁數： | 73/141頁 |
| 文件大小： | 2175K |
| 代理商： | ST7DALI |
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ST7DALI
73/141
DALI COMMUNICATION MODULE
(Cont’d)
11.4.6 Special Functions
11.4.6.1 Forced Transmission (Test mode)
The DCM must receive a "forward frame" before
sending back a "backward frame". But it is possi-
ble to force the DCM into Transmit state by setting
the FTS bit in the DCMCR register. The DCMBD
register will be shifted out in DALI format, the Most
Significant Bit-first. Preferably before forcing the
DCM into Transmit state, the user should reset/set
the DCME bit in the DCMCR register. An interrupt
flag will be generated after a forced transmission
(the ITF bit in the DCMCSR register).
Procedure:
– Reset the DCME bit in the DCMCR register.
– Write the backward value in the DCMBD reg-
ister.
– Set both the DCME and the FTS bits in the
DCMCR register.
– When an interrupt is generated (end of trans-
mission, the ITF bit is set in the DCMCSR reg-
ister), set the RTA bit in the DCMCR register
to re-start a transmission.
– To return to normal DALI communications, re-
set/set the DCME bit and reset the FTS bit in
the DCMCR register.
11.4.6.2 Normal Transmission
After the "forward frame" reception, the software
must write the backward data byte to the DCMBD
register and set both the RTS and RTA bits in the
DCMCR register to start the transmission.
It is not possible to send a backward frame just af-
ter having sent a backward frame (see DALI
standard protocol).
11.4.6.3 DCM Enable
The user can enable or disable the DCM by writing
the DCME bit in the DCMCR register. This bit is
also used to reset the entire internal finite state
machine.
11.4.7 DALI Interface Failure
If the DALI input signal is set to low level for a 2-bit
period (1.66 ms), then the DCM generates an er-
ror flag by setting the EF bit in the DCMCSR regis-
ter. This bit can be cleared by reading the DCMC-
SR register. The interface failure is detected if the
DCM is in Receive state only.
11.4.8 Low Power Modes
11.4.9 Interrupts
Mode
WAIT
HALT
ACTIVE
HALT
Description
No effect on DCM
DCM registers are frozen
No effect on DCM
Interrupt
Event
Event
Flag
Enable
Control
Bit
ITE
Exit
from
Wait
Yes
Exit
from
Halt
No
EOT
ITF
1
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