參數(shù)資料
型號： ST7DALI
廠商： 意法半導體
元件分類： ADC
英文描述： 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI
中文描述： 8位單電壓閃存存儲器，數(shù)據(jù)EEPROM，模數(shù)轉換器，定時器，SPI和大理微控制器
文件頁數(shù)： 33/141頁
文件大小： 2175K
代理商： ST7DALI
ST7DALI
33/141
SYSTEM INTEGRITY MANAGEMENT
(Cont’d)
7.6.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
Reset Value: 0000 0xx0 (0xh)
Bit 7:5 = Reserved, must be kept cleared.
Bit 4 =
WDGRF
Watchdog reset flag
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
Bit 3 =
LOCKED
PLL
Locked Flag
This bit is set and cleared by hardware. It is set au-
tomatically when the PLL reaches its operating fre-
quency.
0: PLL not locked
1: PLL locked
Bit 2 =
LVDRF
LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (by reading). When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Bit 1 =
AVDF
Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit is set. Refer to
Figure
18
and to
Section 7.6.2.1
for additional details.
0: V
DD
over AVD threshold
1: V
DD
under AVD threshold
Bit 0 =
AVDIE
Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag is
set. The pending interrupt information is automati-
cally cleared when software enters the AVD inter-
rupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
7
0
0
0
0
WDG
RF
LOCKED LVDRF AVDF AVDIE
RESET Sources
LVDRF
WDGRF
External RESET pin
Watchdog
LVD
0
0
1
0
1
X
1
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