參數(shù)資料
型號(hào): ST72C171K2
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH 8K FLASH. ADC. WDG. SPI. SCI. TIMERS SPGAS (SOFTWARE PROGRAMMABLE GAIN AMPLIFIERS). OP-AMP
中文描述: 8位8K閃存微控制器。 ADC的。水分散粒劑。的SPI。脊髓損傷。定時(shí)器SPGAS(軟件可編程增益放大器)。運(yùn)放
文件頁(yè)數(shù): 73/152頁(yè)
文件大小: 1384K
代理商: ST72C171K2
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ST72C171
73/152
PWM AUTO-RELOAD TIMER
(Cont’d)
Input capture function
This mode allows the measurement of external
signal pulse widths through ICRx registers.
Each input capture can generate an interrupt inde-
pendently on a selected input signal transition.
This event is flagged by a set of the corresponding
CFx bits of the Input Capture Control/Status regis-
ter (ICCSR).
These input capture interrupts are enabled
through the CIEx bits of the ICCSR register.
The active transition (falling or rising edge) is soft-
ware programmable through the CSx bits of the
ICCSR register.
The read only input capture registers (ICRx) are
used to latch the auto-reload counter value when a
transition is detected on the ARTICx pin (CFx bit
set in ICCSR register). After fetching the interrupt
vector, the CFx flags can be read to identify the in-
terrupt source.
Note
: After a capture detection, data transfer in
the ICRx register is inhibited until it is read (clear-
ing the CFx bit).
The timer interrupt remains pending while the CFx
flag is set when the interrupt is enabled (CIEx bit
set). This means, the ICRx register has to be read
at each capture event to clear the CFx flag.
The timing resolution is given by auto-reload coun-
ter cycle time (1/f
COUNTER
).
Note:
During HALT mode, if both input capture
and external clock are enabled, the ICRx register
value is not guaranteed if the input capture pin and
the external clock change simultaneously.
External interrupt capability
This mode allows the Input capture capabilities to
be used as external interrupt sources. The inter-
rupts are generated on the edge of the ARTICx
signal.
The edge sensitivity of the external interrupts is
programmable (CSx bit of ICCSR register) and
they are independently enabled through CIEx bits
of the ICCSR register. After fetching the interrupt
vector, the CFx flags can be read to identify the in-
terrupt source.
During HALT mode, the external interrupts can be
used to wake up the micro (if the CIEx bit is set).
Figure 46. Input Capture Timing Diagram
04h
COUNTER
t
01h
f
COUNTER
xxh
02h
03h
05h
06h
07h
04h
ARTICx PIN
CFx FLAG
ICRx REGISTER
INTERRUPT
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