參數(shù)資料
型號: ST72C171K2
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH 8K FLASH. ADC. WDG. SPI. SCI. TIMERS SPGAS (SOFTWARE PROGRAMMABLE GAIN AMPLIFIERS). OP-AMP
中文描述: 8位8K閃存微控制器。 ADC的。水分散粒劑。的SPI。脊髓損傷。定時器SPGAS(軟件可編程增益放大器)。運放
文件頁數(shù): 58/152頁
文件大?。?/td> 1384K
代理商: ST72C171K2
ST72C171
58/152
16-BIT TIMER
(Cont’d)
Notes:
1. After a processor write cycle to the OC
i
HR
reg-
ister, the output compare function is inhibited
until the OC
i
LR
register is also written.
2. If the OC
i
E bit is not set, the OCMP
i
pin is a
general I/O port and the OLVL
i
bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is f
CPU
/2, OCF
i
and
OCMP
i
are set while the counter value equals
the OC
i
R register value (see
Figure 8
). This
behaviour is the same in OPM or PWM mode.
When the timer clock is f
CPU
/4, f
CPU
/8 or in
external clock mode, OCF
i
and OCMP
i
are set
while the counter value equals the OC
i
R regis-
ter value plus 1 (see
Figure 9
).
4. The output compare functions can be used both
for generating external events on the OCMP
i
pins even if the input capture mode is also
used.
5. The value in the 16-bit OC
i
R
register and the
OLV
i
bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Forced Compare Output capability
When the FOLV
i
bit is set by software, the OLVL
i
bit is copied to the OCMP
i
pin. The OLV
i
bit has to
be toggled in order to toggle the OCMP
i
pin when
it is enabled (OC
i
E bit=1). The OCF
i
bit is then not
set by hardware, and thus no interrupt request is
generated.
FOLVL
i
bits have no effect in either One-Pulse
mode or PWM mode.
Figure 36. Output Compare Block Diagram
OUTPUT COMPARE
CIRCUIT
16-bit
OC1R
Register
16 BIT
FREE RUNNING
COUNTER
OC1E
CC0
CC1
OC2E
OLVL1
OLVL2
OCIE
(Control Register 1)
CR1
(Control Register 2)
CR2
0
0
0
OCF2
OCF1
(Status Register)
SR
16-bit
16-bit
OCMP1
Pin
OCMP2
Pin
Latch
1
Latch
2
OC2R
Register
FOLV2 FOLV1
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