參數(shù)資料
型號： ST72C171K2
廠商： 意法半導體
英文描述： 8-BIT MCU WITH 8K FLASH. ADC. WDG. SPI. SCI. TIMERS SPGAS (SOFTWARE PROGRAMMABLE GAIN AMPLIFIERS). OP-AMP
中文描述： 8位8K閃存微控制器。 ADC的。水分散粒劑。的SPI。脊髓損傷。定時器SPGAS（軟件可編程增益放大器）。運放
文件頁數(shù)： 132/152頁
文件大小： 1384K
代理商： ST72C171K2
ST72C171
132/152
9.9 CONTROL PIN CHARACTERISTICS
9.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Figure 89. Typical Application with RESET pin
8)
Notes:
1.
Unless otherwise specified, typical data are based on T
A
=25°C and V
DD
=5V.
2. Data based on characterization results, not tested in production.
3.
Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The I
current sunk must always respect the absolute maximum rating specified in
Section 9.2.2
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
5. The R
ON
pull-up equivalent resistor is based on a resistive transistor (corresponding I
current characteristics de-
scribed in
Figure 90
). This data is based on characterization results, not tested in production.
5. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin.
6. All short pulse applied on RESET pin with a duration below t
h(RSTL)in
can be ignored.
7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
environment.
8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Symbol
V
IL
V
IH
V
hys
Parameter
Conditions
Min
Typ
1)
Max
0.3xV
DD
Unit
Input low level voltage
2)
Input high level voltage
2)
Schmitt trigger voltage hysteresis
3)
Output low level voltage
4)
(see
Figure 91
,
Figure 92
)
V
0.7xV
DD
400
0.68
0.28
40
100
6
30
mV
V
OL
V
DD
=5V
I
IO
=+5mA
I
IO
=+2mA
V
DD
=5V
V
DD
=3.4V
0.95
0.45
60
120
V
R
ON
Weak pull-up equivalent resistor
5)
V
IN
=
V
SS
20
80
k
t
w(RSTL)out
Generated reset pulse duration
External pin or
internal reset sources
1/f
SFOSC
μ
s
μ
s
ns
t
h(RSTL)in
t
g(RSTL)in
External reset pulse hold time
6)
Filtered glitch duration
7)
20
100
RESET
V
DD
WATCHDOG RESET
ST72XXX
LVD RESET
INTERNAL
RESET CONTROL
R
ON
0.1
μ
F
V
DD
0.1
μ
F
V
DD
4.7k
EXTERNAL
RESET
CIRCUIT
8)
OPTONAL
USER
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