參數(shù)資料
型號： ST72C171K2
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU WITH 8K FLASH. ADC. WDG. SPI. SCI. TIMERS SPGAS (SOFTWARE PROGRAMMABLE GAIN AMPLIFIERS). OP-AMP
中文描述： 8位8K閃存微控制器。 ADC的。水分散粒劑。的SPI。脊髓損傷。定時(shí)器SPGAS（軟件可編程增益放大器）。運(yùn)放
文件頁數(shù)： 126/152頁
文件大小： 1384K
代理商： ST72C171K2
ST72C171
126/152
EMC CHARACTERISTICS
(Cont’d)
9.7.2.2 Static and Dynamic Latch-Up
– LU: 3 complementary static tests are required on
10 parts to assess the latch-up performance. A
supply overvoltage (applied to each power sup-
ply pin), a current injection (applied to each input,
output and configurable I/O pin) and a power
supply switch sequence are performed on each
sample. This test conforms to the EIA/JESD 78
IC latch-up standard. For more details, refer to
the AN1181 ST7 application note.
– DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin of
3 samples when the micro is running to assess
the latch-up performance in dynamic mode.
Power supplies are set to the typical values, the
oscillator is connected as near as possible to the
pins of the micro and the component is put in re-
set mode. This test conforms to the IEC1000-4-2
and SAEJ1752/3 standards and is described in
Figure 75
. For more details, refer to the AN1181
ST7 application note.
Electrical Sensitivities
Figure 75. Simplified Diagram of the ESD Generator for DLU
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
Symbol
Parameter
Conditions
Class
1)
LU
Static latch-up class
T
A
=
+25°C
T
A
=
+85°C
V
DD
=
5.5V, f
OSC
=
4MHz, T
A
=
+25°C
A
A
A
DLU
Dynamic latch-up class
R
CH
=50M
R
D
=330
C
S
=
150pF
ESD
GENERATOR
2)
HV RELAY
DISCHARGE TIP
DISCHARGE
RETURN CONNECTION
ST7
V
DD
V
SS
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