參數(shù)資料
型號： ST72C171K2
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU WITH 8K FLASH. ADC. WDG. SPI. SCI. TIMERS SPGAS (SOFTWARE PROGRAMMABLE GAIN AMPLIFIERS). OP-AMP
中文描述： 8位8K閃存微控制器。 ADC的。水分散粒劑。的SPI。脊髓損傷。定時(shí)器SPGAS（軟件可編程增益放大器）。運(yùn)放
文件頁數(shù)： 36/152頁
文件大?。?/td> 1384K
代理商： ST72C171K2
ST72C171
36/152
7.2 MISCELLANEOUS REGISTERS
7.2.1 Miscellaneous Register 1 (MISCR1)
Miscellaneous register 1 is used select SLOW op-
erating mode. Bits 3, 4, 6, and 7 determine the po-
larity of external interrupt requests.
Register Address: 0020h
Reset Value: 0000 0000 (00h)
—
Read/Write
Bit 7:6 =
PEI[3:2]
Polarity Options of External In-
terrupt ei1. (Port B)
.
These bits are set and cleared by software. These
bits determine which event causes the external in-
terrupt (ei1) on port B according to
Table 8
.
Table 8. ei1 Ext. Int. Polarity Options
Bit 5 =
MCO
Main clock out selection
This bit enables the MCO alternate function on the
I/O port. It is set and cleared by software.
0: MCO alternate function disabled
(I/O pin free for general-purpose I/O)
1: MCO alternate function enabled
(f
OSC
/2 on I/O port)
This bit is set and cleared by software. When set it
can be used to output the internal clock to the ded-
icated I/O port.
Bit 4:3 =
PEI[1:0]
Polarity Options of External In-
terrupt ei0. (Port A)
These bits determine which event causes the ex-
ternal interrupt (ei0) on port A according to
Table
9
.
Table 9. ei0 Ext. Int. Polarity Options
Bit 2:1 =
CP[1:0]
CPU clock prescaler
These bits are set and cleared by software. They
determine the CPU clock when the SMS bit is set
according to the following table.
Table 10. f
CPU
Value in Slow Mode
f
CPU
Value
f
OSC
/ 4
f
OSC
/ 8
f
OSC
/ 16
f
OSC
/ 32
Bit 0 =
SMS
Slow Mode Select
This bit is set and cleared by software.
0: Normal Mode - f
CPU
= f
OSC
/ 2
1: Slow Mode - the f
CPU
value is determined by the
PC[1:0] bits.
7
0
PEI3
PEI2
MCO PEI1 PEI0 CP1
CP0
SMS
MODE
PEI3
PEI2
Falling edge and low level
(Reset state)
0
0
Rising edge only
0
1
Falling edge only
1
0
Rising and falling edge
1
1
MODE
PEI1
PEI0
Falling edge and low level
(Reset state)
0
0
Rising edge only
0
1
Falling edge only
1
0
Rising and falling edge
1
1
CP1
CP0
0
0
1
0
0
1
1
1
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