參數(shù)資料
型號(hào)： ST72C171K2
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU WITH 8K FLASH. ADC. WDG. SPI. SCI. TIMERS SPGAS (SOFTWARE PROGRAMMABLE GAIN AMPLIFIERS). OP-AMP
中文描述： 8位8K閃存微控制器。 ADC的。水分散粒劑。的SPI。脊髓損傷。定時(shí)器SPGAS（軟件可編程增益放大器）。運(yùn)放
文件頁數(shù)： 70/152頁
文件大?。?/td> 1384K
代理商： ST72C171K2
ST72C171
70/152
PWM AUTO-RELOAD TIMER
(Cont’d)
7.6.2 Functional Description
Counter
The free running 8-bit counter is fed by the output
of the prescaler, and is incremented on every ris-
ing edge of the clock signal.
It is possible to read or write the contents of the
counter on the fly by reading or writing the Counter
Access register (CAR).
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the
ARR register (the prescaler is not affected).
Counter clock and prescaler
The counter clock frequency is given by:
f
COUNTER
= f
INPUT
/ 2
CC[2:0]
The timer counter’s input clock (f
INPUT
) feeds the
7-bit programmable prescaler, which selects one
of the 8 available taps of the prescaler, as defined
by CC[2:0] bits in the Control/Status Register
(CSR). Thus the division factor of the prescaler
can be set to 2
n
(where n = 0, 1,..7).
This f
INPUT
frequency source is selected through
the EXCL bit of the CSR register and can be either
the f
CPU
or an external input frequency f
EXT
.
The clock input to the counter is enabled by the
TCE (Timer Counter Enable) bit in the CSR regis-
ter. When TCE is reset, the counter is stopped and
the prescaler and counter contents are frozen.
When TCE is set, the counter runs at the rate of
the selected clock source.
Counter and Prescaler Initialization
After RESET, the counter and the prescaler are
cleared and f
INPUT
= f
CPU
.
The counter can be initialized by:
– Writing to the ARR register and then setting the
FCRL (Force Counter Re-Load) and the TCE
(Timer Counter Enable) bits in the CSR register.
– Writing to the CAR counter access register,
In both cases the 7-bit prescaler is also cleared,
whereupon counting will start from a known value.
Direct access to the prescaler is not possible.
Output compare control
The timer compare function is based on four differ-
ent comparisons with the counter (one for each
PWMx output). Each comparison is made be-
tween the counter value and an output compare
register (OCRx) value. This OCRx register can not
be accessed directly, it is loaded from the duty cy-
cle register (DCRx) at each overflow of the coun-
ter.
This double buffering method avoids glitch gener-
ation when changing the duty cycle on the fly.
Figure 42. Output compare control
COUNTER
FDh
FEh
FFh
FDh
FEh
FFh
FDh
FEh
ARR=FDh
f
COUNTER
OCRx
DCRx
FDh
FEh
FDh
FEh
FFh
PWMx
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ST72C215G2M3 制造商:STMicroelectronics 功能描述:MCU 8-Bit ST7 CISC 8KB Flash 3.3V/5V 28-Pin SO Tube 制造商:STMicroelectronics 功能描述:MCU 8BIT ST7 CISC 8KB FLASH 3.3V/5V 28SOIC - Rail/Tube
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