參數(shù)資料
型號： ST72C171K2
廠商： 意法半導體
英文描述： 8-BIT MCU WITH 8K FLASH. ADC. WDG. SPI. SCI. TIMERS SPGAS (SOFTWARE PROGRAMMABLE GAIN AMPLIFIERS). OP-AMP
中文描述： 8位8K閃存微控制器。 ADC的。水分散粒劑。的SPI。脊髓損傷。定時器SPGAS（軟件可編程增益放大器）。運放
文件頁數(shù)： 18/152頁
文件大小： 1384K
代理商： ST72C171K2
ST72C171
18/152
RESET SEQUENCE MANAGER
(Cont’d)
4.2.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R
ON
weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It
can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
A RESET signal originating from an external
source must have a duration of at least t
h(RSTL)in
in
order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
Two RESET sequences can be associated with
this RESET source: short or long external reset
pulse (see
Figure 12
).
Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least t
w(RSTL)out
.
4.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
I
Power-On RESET
I
Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when V
DD
<V
IT+
(rising edge) or
V
DD
<V
IT-
(falling edge) as shown in
Figure 12
.
The LVD filters spikes on V
DD
larger than t
g(VDD)
to
avoid parasitic resets.
4.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in
Figure 12
.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
w(RSTL)out
.
Figure 12. RESET Sequences
V
DD
RUN
RESET PIN
EXTERNAL
RESET
SOURCE
WATCHDOG
RESET
DELAY
V
IT+
V
IT-
t
h(RSTL)in
t
w(RSTL)out
RUN
DELAY
t
h(RSTL)in
DELAY
WATCHDOG UNDERFLOW
t
w(RSTL)out
RUN
RUN
DELAY
RUN
SHORT EXT.
RESET
LVD
RESET
LONG EXT.
RESET
WATCHDOG
RESET
INTERNAL RESET (4096 T
CPU
)
FETCH VECTOR
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