參數(shù)資料
型號: ST72C171K2
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH 8K FLASH. ADC. WDG. SPI. SCI. TIMERS SPGAS (SOFTWARE PROGRAMMABLE GAIN AMPLIFIERS). OP-AMP
中文描述: 8位8K閃存微控制器。 ADC的。水分散粒劑。的SPI。脊髓損傷。定時器SPGAS(軟件可編程增益放大器)。運放
文件頁數(shù): 127/152頁
文件大?。?/td> 1384K
代理商: ST72C171K2
ST72C171
127/152
EMC CHARACTERISTICS
(Cont’d)
9.7.3 ESD Pin Protection Strategy
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.
An ESD network combines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in
Figure 76
and
Figure 77
for standard
pins and in
Figure 78
and
Figure 79
for true open
drain pins.
Standard Pin Protection
To protect the output structure the following ele-
ments are added:
– A diode to V
DD
(3a) and a diode from V
SS
(3b)
– A protection device between V
DD
and V
SS
(4)
To protect the input structure the following ele-
ments are added:
– A resistor in series with the pad (1)
– A diode to V
DD
(2a) and a diode from V
SS
(2b)
– A protection device between V
DD
and V
SS
(4)
Figure 76. Positive Stress on a Standard Pad vs. V
SS
Figure 77. Negative Stress on a Standard Pad vs. V
DD
IN
V
DD
V
SS
(1)
(2a)
(2b)
(4)
OUT
V
DD
V
SS
(3a)
(3b)
Main path
Path to avoid
IN
V
DD
V
SS
(1)
(2a)
(2b)
(4)
OUT
V
DD
V
SS
(3a)
(3b)
Main path
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