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參數(shù)資料
| 型號： | ST52X420 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | ADC |
| 英文描述： | 8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Three Timer/PWMs, ADC, WDG |
| 中文描述： | 8位智能控制器病房（ICU）3個定時器/的PWM，ADC的，水分散粒劑 |
| 文件頁數(shù)： | 52/84頁 |
| 文件大?。?/td> | 1274K |
| 代理商： | ST52X420 |
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ST52T410/ST52T420/E420
52/84
10 PWM/TIMER
ST52T410/ST52x420 offers three on-chip PWM/
Timer peripherals:TIMER0, TIMER1 and TIMER2.
The ST52T410/ST52x420 timers have the same
internal structure. The timer consists of an 8-bit
counter with a 16-bit programmable prescaler,
giving a maximum count of 2
24
(see Figure 10.1).
Figure 10.1 Timer Peripheral Block Diagram
Next, the generic timer is called Timer x, where x
can be 0, 1 or 2.
Each timer has two different working modes, which
can be selected by setting the correspondent
TxMODE bits of REG_CONF5, REG_CONF8 and
REG_CONF10 registers: Timer Mode and PWM
(Pulse Width Modulation) Mode.
All Timers have Autoreload Functions in PWM
Mode.
Each
timer
output
is
complementary signal on external pins by setting
PAx and PCx bits of REG_CONF12 and
REG_CONF16 (see Table 10.8 and Table 10.9).
Note: In order to enable timer output (TxOUT or
TxOUT) the related pin must be configured in
Output Mode by setting REG_CONF4 and
REG_CONF15 registers (see Table 7.4 and
Table 7.6)
In particular, TIMER0 can also use external
START/STOP signals (Input capture and Output
compare), external RESET signal and external
CLOCK: PA4/T0STRT, PA0/T0RES and PA5/
T0CLK pins.
available,
with
its
Note: In order to use T0RST, T0STR, T0CLK
external signals the related pins must be
configured
in
Input
REG_CONF4 and REG_CONF7 registers (see
Table 7.4 and Table 10.3)
For each timer, the content of the 8-bit counter is
incremented on the Rising Edge of the 16-bit
prescaler output (PRESCOUT) and it can be read
at any instant of the counting phase, saved in a
location of RAM memory. The PWM/Timer x
Counter value can be read from the Input Register
Mode
by
setting
PWM_x_COUNT (Input Registers 12, 14 or 16.
See Table 2.2).
The PWM/Timer x Status can be read from the
Input Register PWM_x_STATUS (Input Registers
13, 15 or 17. See Table 2.2 and Table 10.10).
10.1 Timer Mode
Timer Mode is selected by fixing the TxMODE bit
of
REG_CONF5,
REG_CONF10 equal to 0 (see Table 10.1, Table
10.4 and Table 10.6).
Each TIMERx requires three signals: Timer Clock
(TMRCLKx), Timer Reset (TxRES) and Timer Start
(TxSTRT) (see Figure 10.1). Each of these signals
can be generated internally, or, only for Timer 0,
externally by setting T0RST, T0STR, T0CLK bits of
REG_CONF7 register.
TMRCLKx is the Prescaler x output, which
increments the Counter x value on the rising edge.
TMRCLKx is obtained from the internal clock
signal (CLKM) or, only for TIMER0, from the
external signal provided on the PA5/T0CLK pin.
REG_CONF8
and
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 14
BIT 15
BIT 3
BIT 0
BIT 1
BIT 2
BIT 6
BIT 4
BIT 5
BIT 7
17 - 1 MULTIPLEXER
16-BIT PRESCALER
8-BIT COUNTER
PRESCx
CLKM
TMRCLK
TxRES
TxSTRT
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